rtl-p5s-uvm-verify

What problem does it solve?

This skill automates running UVM-based verification on RTL when projects require commercial simulators, removing manual orchestration of compile, multi-seed regression runs, and coverage merging so verification teams can obtain deterministic reports and coverage artifacts quickly.

Core Features & Use Cases

• Multi-seed regression orchestration: compile the UVM testbench, dispatch multiple random-seed runs in parallel, and collect per-seed results.
• Commercial simulator support: integrates with VCS, Xcelium (xrun), and Questa (vsim) and selects appropriate compile/run flows.
• Coverage merge and reporting: merges simulator coverage outputs into a consolidated coverage artifact and generates a regression summary with pass/fail statistics and failed-seed listings.
• Use Case: run constrained-random UVM tests across many seeds, halt early on high failure rate, and produce merged code and functional coverage for signoff.

Quick Start

Run a multi-seed UVM regression for module top using the commercial simulator vcs and collect merged coverage.