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rtl-p5s-uvm-policy

Enforce UVM naming, coverage, regression, and escalation policies for verification flows.

43|9|Updated Feb 25, 2026
Search Tags:#verification#regression#coverage#simulator#naming-conventions#uvm#coverage-driven
One-click install
npx skills add https://github.com/babyworm/rtl-agent-team --skill rtl-p5s-uvm-policy
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: rtl-p5s-uvm-policy
Source: https://github.com/babyworm/rtl-agent-team/tree/main/skills/rtl-p5s-uvm-policy
Command: npx skills add https://github.com/babyworm/rtl-agent-team --skill rtl-p5s-uvm-policy

SYSTEM DOCUMENTATION & REQUIREMENTS

What problem does it solve?

This policy document reduces wasted simulation time and inconsistent verification results by standardizing UVM naming, coverage collection, regression orchestration, and escalation rules so teams run reproducible, measurable regressions.

Core Features & Use Cases

  • Naming & coding conventions: Enforces DUT instance and signal naming, UVM member prefixes, and SystemVerilog declaration style to ensure testbenches and RTL connect cleanly.
  • Coverage targets & tool flags: Specifies line, toggle, FSM, branch, and functional coverage targets and the exact simulator flags and merge steps required for VCS, Questa, and Xcelium.
  • Coverage-driven verification loop: Defines a 3-round CDV feedback process with gap analysis, directed test generation, coverage merging, and convergence detection.
  • Stimulus connectivity and enforcement: Describes randomization and DUT connectivity checks with thresholds to detect ineffective stimuli and halt regressions for debugging.
  • Regression runner and stop conditions: Details how to run multi-seed regressions, merge coverage, and escalate on missing commercial simulators, compile errors, or scoreboard mismatches.

Quick Start

Run a coverage-driven UVM regression for your module, merge seed results, and generate a consolidated coverage report for analysis.

Frequently Asked Questions about rtl-p5s-uvm-policy

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I merge coverage from multi-seed UVM regressions across different commercial simulators?▼

UVM naming conventions enforce DUT instance and signal naming, UVM member prefixes, and SystemVerilog declaration style. This ensures testbenches and RTL connect cleanly, reducing wasted simulation time and inconsistent verification results during regressions.

What is a coverage-driven verification loop and when do I need convergence gates?▼

Convergence gates detect when coverage stops improving and trigger explicit stop or escalation conditions. This prevents wasted simulation time by halting regressions for debugging when stimulus connectivity checks fall below defined thresholds or scoreboard mismatches occur.

Does this UVM policy support VCS, Questa, and Xcelium simulators for coverage collection?▼

The policy specifies exact coverage collection flags and merge steps for VCS, Questa, and Xcelium. It enforces line, toggle, FSM, branch, and functional coverage targets, ensuring consistent coverage collection and reproducible regression results across commercial simulators.

How do I enforce stimulus connectivity checks and randomization thresholds in a UVM testbench?▼

You enforce stimulus connectivity by applying randomization and DUT connectivity checks with defined thresholds. These checks detect ineffective stimuli during coverage-driven regressions and halt the pipeline for debugging before wasting simulation time.

When should regressions escalate and stop in a coverage-driven UVM verification flow?▼

Regressions should escalate and stop when explicit conditions are met, including missing commercial simulators, compile errors, or scoreboard mismatches. The policy defines these stop conditions to prevent wasting simulation time on broken verification pipelines.

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