rtl-p5s-uvm-policy

What problem does it solve?

This policy document reduces wasted simulation time and inconsistent verification results by standardizing UVM naming, coverage collection, regression orchestration, and escalation rules so teams run reproducible, measurable regressions.

Core Features & Use Cases

• Naming & coding conventions: Enforces DUT instance and signal naming, UVM member prefixes, and SystemVerilog declaration style to ensure testbenches and RTL connect cleanly.
• Coverage targets & tool flags: Specifies line, toggle, FSM, branch, and functional coverage targets and the exact simulator flags and merge steps required for VCS, Questa, and Xcelium.
• Coverage-driven verification loop: Defines a 3-round CDV feedback process with gap analysis, directed test generation, coverage merging, and convergence detection.
• Stimulus connectivity and enforcement: Describes randomization and DUT connectivity checks with thresholds to detect ineffective stimuli and halt regressions for debugging.
• Regression runner and stop conditions: Details how to run multi-seed regressions, merge coverage, and escalate on missing commercial simulators, compile errors, or scoreboard mismatches.

Quick Start

Run a coverage-driven UVM regression for your module, merge seed results, and generate a consolidated coverage report for analysis.