chipyard-rtl

Generate synthesizable Verilog RTL from local Chipyard Rocket Chip configurations.

2|Updated Mar 16, 2026

Search Tags:#rtl #hardware-design #verilog #chisel #chipyard #rocket-chip #verilog-generation

Ready to run

npx skills add https://github.com/xsw632/ChipAgent --skill chipyard-rtl

💬 Prompt for ChatGPT / Claude Chat▼

Please help me install this Agent Skill.
Skill: chipyard-rtl
Source: https://github.com/xsw632/ChipAgent/tree/main/skills/chipyard-rtl
Command: npx skills add https://github.com/xsw632/ChipAgent --skill chipyard-rtl

SYSTEM DOCUMENTATION & REQUIREMENTS

What problem does it solve?

Manually elaborating Chipyard Rocket Chip configurations to generate Verilog RTL is time-consuming and error-prone, especially for hardware designers working on custom SoC projects.

Core Features & Use Cases

Automated RTL Generation: Elaborates Rocket Chip configurations (e.g. TinyRocketConfig) from a local Chipyard installation to produce split, synthesizable Verilog files.
Artifact Verification: Automatically locates and validates generated output including top-level modules, Verilog file counts, and memory configuration files.
Use Case: Hardware engineers can quickly generate production-ready RTL for Chipyard-based SoCs without manually executing complex sbt and firtool build commands.

Quick Start

Use the chipyard-rtl skill to generate split Verilog RTL files from your local Chipyard installation using the default TinyRocketConfig.

Frequently Asked Questions about chipyard-rtl

High-intent search queries and answers about installing and using this skill.

FAQPage Schema

How do I generate Verilog RTL from a local Chipyard Rocket Chip configuration?▼

To generate Verilog RTL from Chipyard, this skill automates the elaboration of Rocket Chip configurations like TinyRocketConfig into split, synthesizable Verilog files without manually executing sbt or firtool build commands. It validates the local installation and toolchain dependencies before running the generation pipeline and verifying output artifacts.

What is the process of elaborating Chisel configurations into synthesizable Verilog?▼

Elaborating Chisel configurations into synthesizable Verilog involves validating the local Chipyard environment, processing custom SoC configuration classes, and using firtool to produce split Verilog output files. The skill streamlines this mechanism by automatically verifying build dependencies and locating the generated top-level modules.

Do I need to manually run sbt and firtool commands to produce Verilog from Chipyard?▼

You do not need to manually run sbt and firtool commands to produce Verilog from Chipyard. The skill completely automates the build command execution, validating the specified configuration class and toolchain dependencies to directly generate production-ready Verilog files.

Can I use this to generate Verilog for custom Rocket Chip-based SoCs?▼

You can use this to generate Verilog for custom Rocket Chip-based SoCs by specifying your custom Chisel configuration class. The skill validates the Chipyard installation and required toolchain dependencies before elaborating the configuration into synthesizable Verilog files.

How does the skill verify the generated Chipyard Verilog output artifacts?▼

The skill verifies generated Chipyard Verilog output artifacts by automatically locating and validating the top-level modules, counting the generated Verilog files, and checking the memory configuration files. This ensures the Rocket Chip configuration elaboration produced complete and usable RTL.

Why does manually generating RTL from Chipyard configurations cause errors?▼

Manually generating RTL from Chipyard configurations causes errors due to complex sbt and firtool build commands and missing toolchain dependencies. The skill resolves this by validating the local installation and automating the Verilog generation pipeline to prevent manual execution mistakes.