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sram-mapping

Analyze Verilog RTL to map SRAM instances to sky130hd macros.

2|Updated Mar 16, 2026
Search Tags:#asic#verilog#place-and-route#sram-mapping#sky130hd#memory-macro#rtl-analysis
One-click install
npx skills add https://github.com/xsw632/ChipAgent --skill sram-mapping
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: sram-mapping
Source: https://github.com/xsw632/ChipAgent/tree/main/skills/sram-mapping
Command: npx skills add https://github.com/xsw632/ChipAgent --skill sram-mapping

SYSTEM DOCUMENTATION & REQUIREMENTS

What problem does it solve?

Manually identifying SRAM instances in Verilog RTL and determining their correct mapping to sky130hd process SRAM macros or standard-cell alternatives is time-consuming, error-prone, and requires deep familiarity with both the RTL design and the target process's memory macro library. This skill automates that entire analysis workflow for ASIC design teams, reducing mapping time from hours to minutes and eliminating costly manual errors.

Core Features & Use Cases

  • Automated SRAM Instance Identification: Scans Verilog/SystemVerilog RTL to detect behavioral memory arrays, SRAM macro wrappers, register files, and FIFO buffers, extracting key attributes like depth, width, and port types.
  • Full Hierarchy Tracing: Builds complete instantiation chains from leaf memory modules up to the top-level design to provide critical context for floorplanning and physical design workflows.
  • Intelligent Mapping Calculation: Enumerates available sky130hd SRAM macros and computes the optimal mapping strategy for each memory instance, including direct macro matches, multi-macro depth/width tiling, or standard-cell DFF implementations for incompatible or small memories.
  • Real-World Use Case: For a RISC-V SoC design targeting the sky130hd open-source process, use this skill to analyze generated Verilog collateral and produce the SRAM mapping configuration required for place-and-route, eliminating hours of manual cross-referencing of memory specs and macro libraries.

Quick Start

Use the sram-mapping skill to analyze your Verilog RTL directory or single file and generate a complete SRAM mapping report and configuration file ready for sky130hd place-and-route.

Frequently Asked Questions about sram-mapping

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I automate SRAM macro mapping for sky130hd Verilog RTL?▼

Automating SRAM macro mapping for sky130hd Verilog RTL requires analyzing SystemVerilog code to detect memory arrays and FIFO buffers, then computing optimal mapping strategies. This skill traces hierarchy context to generate structured configurations for downstream place-and-route tools.

What is the best way to identify SRAM instances in SystemVerilog for ASIC design?▼

Identifying SRAM instances in SystemVerilog for ASIC design involves scanning RTL to detect behavioral memory arrays, register files, and FIFO modules, extracting attributes like depth, width, and port types. Full hierarchy tracing provides critical floorplanning context for physical design.

Can I map behavioral memory arrays to standard-cell flip-flops instead of hard macros in sky130hd?▼

Mapping behavioral memory arrays to standard-cell flip-flops in sky130hd is supported when memories are incompatible with available hard macros or too small. The tool intelligently calculates whether to use direct macro matches, multi-macro tiling, or DFF implementations.

How do I generate place-and-route configurations for memory tiling in sky130hd?▼

Generating place-and-route configurations for memory tiling in sky130hd requires enumerating available SRAM macros and computing multi-macro depth or width tiling strategies. The skill outputs structured mapping configurations with macro assignments and hierarchy context for automated physical design tools.

Does this SRAM mapping approach work with RISC-V SoC RTL targeting the sky130hd process?▼

This SRAM mapping approach works with RISC-V SoC RTL targeting the sky130hd process by analyzing generated Verilog collateral to produce required SRAM mapping configurations. It eliminates hours of manual cross-referencing of memory specifications and macro libraries.

When should I not use automated SRAM macro mapping for my ASIC design?▼

Automated SRAM macro mapping for ASIC design is not suitable for processes other than sky130hd, as it specifically targets the open-source sky130hd macro library. Designs requiring custom memory compilers or non-standard macro architectures would need alternative mapping approaches.

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