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chipyard-docker

Generate Verilog RTL from Chipyard configs using Docker containers.

2|Updated Mar 16, 2026
Search Tags:#docker#verilog#hardware design#place-and-route#rtl generation#chipyard#sram mapping
One-click install
npx skills add https://github.com/xsw632/ChipAgent --skill chipyard-docker
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: chipyard-docker
Source: https://github.com/xsw632/ChipAgent/tree/main/skills/chipyard-docker
Command: npx skills add https://github.com/xsw632/ChipAgent --skill chipyard-docker

SYSTEM DOCUMENTATION & REQUIREMENTS

What problem does it solve?

Setting up a local Chipyard environment with Chisel, sbt, and FIRRTL to generate RTL from hardware configurations is complex and error-prone. Manually staging generated artifacts and creating SRAM mappings for place-and-route adds further overhead to hardware design workflows.

Core Features & Use Cases

  • Dockerized RTL Generation: Produce Verilog from Chipyard configs (e.g., TinyRocket) without installing local hardware design toolchains.
  • Automated SRAM Mapping: Analyze generated memory modules and map them to sky130hd standard SRAM macros for the target process.
  • Artifact Staging: Automatically organize generated Verilog, memory configs, and design specs into the ChipAgent workspace for downstream PnR workflows.
  • Use Case: A hardware engineer can generate production-ready RTL for a custom RISC-V core in minutes, with pre-validated memory mappings, and immediately hand off the design to the place-and-route team.

Quick Start

Use the chipyard-docker skill to generate RTL from a Chipyard configuration and stage all required artifacts for the place-and-route workflow.

Frequently Asked Questions about chipyard-docker

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I generate RTL from Chipyard configurations without installing local toolchains?▼

You can generate RTL from Chipyard configurations without local toolchains by using a Dockerized environment. This approach containerizes Chisel, sbt, and FIRRTL dependencies to produce Verilog source files directly from RISC-V hardware configs.

How does automated SRAM mapping work for sky130hd Verilog?▼

Automated SRAM mapping for sky130hd Verilog analyzes generated memory modules and maps them to standard SRAM macros. This process creates memory mapping JSON configurations required for downstream place-and-route integration.

Do I need to install Chisel or sbt locally to produce Verilog for RISC-V cores?▼

No, you do not need to install Chisel or sbt locally to produce RISC-V Verilog. The containerized Docker environment eliminates local dependency installation requirements by pre-packaging the necessary hardware design toolchains.

What is the best way to stage Verilog artifacts for a place-and-route workflow?▼

The best way to stage Verilog artifacts for place-and-route is through automated artifact staging. This organizes generated Verilog source files, memory configs, and design specs into a structured workspace for immediate PnR handoff.

Can I use Chipyard Docker for sky130hd SRAM macro mapping and PnR preparation?▼

Yes, you can use Chipyard Docker for sky130hd SRAM macro mapping and PnR preparation. It generates RTL, maps memory modules to sky130hd standard SRAM macros, and stages all required design specification metadata for the PnR pipeline.

Why does manual RTL generation and artifact staging add overhead to hardware design?▼

Manual RTL generation and artifact staging add overhead because setting up local Chipyard environments with Chisel and FIRRTL is complex and error-prone. Manually creating SRAM mappings for place-and-route further increases workflow overhead.

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