Run Chipyard RTL-to-GDS place-and-route flows in Docker containers.
npx skills add https://github.com/xsw632/ChipAgent --skill chipyard-pnr-docker
Please help me install this Agent Skill. Skill: chipyard-pnr-docker Source: https://github.com/xsw632/ChipAgent/tree/main/skills/chipyard-pnr-docker Command: npx skills add https://github.com/xsw632/ChipAgent --skill chipyard-pnr-docker
Running Chipyard-generated RTL through the ORFS place-and-route flow traditionally requires local installation of complex EDA toolchains, manual SRAM macro replacement, and iterative parameter tuning to meet timing, area, and power targets — all of which are time-consuming and error-prone for hardware designers.
Use the chipyard-pnr-docker skill to run a full place-and-route flow for your Chipyard RISC-V design and receive an optimized GDS layout with timing, area, and power reports.
High-intent search queries and answers about installing and using this skill.
You can run the Chipyard RISC-V place-and-route flow entirely within Docker containers, eliminating the need for local Chipyard or ORFS installations. This approach manages all tool execution internally to produce optimized layout artifacts.
To fix out-of-memory errors during sky130hd routing, you can use automated SRAM macro handling. This process replaces behavioral SRAM stubs with sky130_sram macros before routing, preventing memory exhaustion and ensuring successful layout generation.
Adaptive tuning for timing closure works by automatically adjusting clock period, utilization, and placement parameters over multiple rounds. It iteratively compares results round-by-round to meet timing and routability goals for your design.
No, you do not need local OpenROAD or Chipyard installations to generate a GDS layout for sky130hd. The entire RTL-to-GDS place-and-route flow executes inside managed Docker containers without requiring local EDA dependencies.
Yes, you can automate multi-clock constraint generation for Chipyard RISC-V designs in Docker. The flow handles constraint generation automatically, alongside SRAM macro replacement and iterative parameter tuning, to produce final GDS, SPEF, and Verilog netlists.
xsw632Generate Verilog RTL from Chipyard configs using Docker containers.
ShenShan123Automate EDA signoff from RTL to GDS with DRC, LVS, and RCX verification.
xsw632Analyze Verilog RTL to map SRAM instances to sky130hd macros.
xsw632Automates Chipyard-to-GDSII place-and-route for sky130hd using OpenROAD Flow Scripts.
