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chipyard-local

Automate Chipyard Verilog generation and sky130hd SRAM mapping for OpenROAD.

2|Updated Mar 16, 2026
Search Tags:#verilog#risc-v#pnr#place-and-route#sram-mapping#chipyard#hardware-generation
One-click install
npx skills add https://github.com/xsw632/ChipAgent --skill chipyard-local
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: chipyard-local
Source: https://github.com/xsw632/ChipAgent/tree/main/skills/chipyard-local
Command: npx skills add https://github.com/xsw632/ChipAgent --skill chipyard-local

SYSTEM DOCUMENTATION & REQUIREMENTS

What problem does it solve?

Manually executing the local Chipyard hardware generation pipeline is tedious and error-prone, requiring precise environment setup, RTL generation, SRAM macro mapping, and correct artifact staging for physical implementation tools.

Core Features & Use Cases

  • End-to-end local Chipyard flow: Automates Verilog generation from a local Chipyard installation for any valid config, with upfront environment and config validation to catch errors early.
  • Automated sky130hd SRAM mapping: Analyzes generated RTL memories, applies priority-based mapping rules to assign compatible sky130hd SRAM macros or standard-cell DFFs, and outputs the required mapping configuration for place-and-route.
  • Use case: Hardware engineers developing Chipyard-based RISC-V processors can use this skill to quickly prepare verified, correctly staged RTL and memory metadata for OpenROAD physical implementation, eliminating manual file manipulation and configuration mistakes.

Quick Start

Use the chipyard-local skill with your target Chipyard config name to automatically generate RTL, compute SRAM mappings, and stage all required artifacts for downstream place-and-route.

Frequently Asked Questions about chipyard-local

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I automate Verilog generation and SRAM mapping for a local Chipyard RISC-V config?▼

To automate Verilog generation and SRAM mapping for a local Chipyard RISC-V config, use this skill to validate environments, run make verilog, and apply priority-based sky130hd SRAM macro mapping automatically. It eliminates manual RTL generation and artifact staging errors.

What is the process for preparing Chipyard RTL for OpenROAD place-and-route?▼

The process for preparing Chipyard RTL for OpenROAD place-and-route involves generating flattened Verilog, computing priority-based memory mapping strategies, and staging all PnR metadata and artifacts for physical implementation. This ensures correct downstream handoff.

Can I use sky130hd SRAM macros with my generated Chipyard Verilog?▼

Yes, you can use sky130hd SRAM macros with generated Chipyard Verilog. This skill analyzes RTL memories and applies priority-based mapping rules to assign compatible sky130hd SRAM macros or standard-cell DFFs automatically, outputting required PnR configurations.

Do I need a local Chipyard installation to generate RISC-V hardware for physical implementation?▼

Yes, you need a local Chipyard installation to generate RISC-V hardware for physical implementation. The skill validates your Chipyard and ORFS environment setup upfront before executing the make verilog flow to catch configuration errors early.

Why does my manual Chipyard RTL staging fail during physical implementation?▼

Your manual Chipyard RTL staging may fail during physical implementation due to incorrect environment setup, missing SRAM macro mapping, or improperly staged PnR metadata that this automated workflow validates and resolves upfront.

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