p2-arch-design-policy

What problem does it solve?

Provides a formalized Phase 2 architecture review policy to ensure hardware candidate evaluation, memory and bandwidth feasibility, naming consistency, and convergent review outcomes so that architectural decisions are measurable, auditable, and aligned with upstream requirements.

Core Features & Use Cases

• Structured Review Criteria: Gate checks for gate count, critical path, SRAM needs, external bandwidth, throughput, and implementation risk.
• Dynamic Convergence Protocol: Iterative review rounds with mandatory reviewers, rebuttal workflow, convergence metrics, and escalation paths.
• Memory & Bandwidth Analysis: Classification of local/cross-domain/external memory, latency assumptions, bandwidth_report.json consumption, and mitigation strategies.
• Compliance & Traceability: OPEN-1* resolution, iron-requirements generation, ambiguity scoring, and automated compliance-checker integration with upstream Phase 1.
• Artifact Requirements: Templates and required outputs like hw-candidate-review.md, wonder-log.md, per-round review artifacts, and ADRs for key decisions.
• Use case: Evaluate multiple algorithmic candidates for a codec block, estimate PPA tradeoffs, select a candidate with documented rationale, and record compliance evidence for Phase 2 exit.

Quick Start

Use the p2-arch-design-policy skill to generate a Phase 2 architecture review checklist, classify memory and bandwidth requirements, and produce the initial wonder-log entry for the current design.