rtl-lint-check

Lints RTL files using Verilator, Verible, slang, and a custom convention checker across rtl/ and sim/ directories.

43|9|Updated Feb 25, 2026

Search Tags:#lint #coding-conventions #rtl #verilator #verilog #slang #verible

Ready to run

npx skills add https://github.com/babyworm/rtl-agent-team --skill rtl-lint-check

💬 Prompt for ChatGPT / Claude Chat▼

Please help me install this Agent Skill.
Skill: rtl-lint-check
Source: https://github.com/babyworm/rtl-agent-team/tree/main/skills/rtl-lint-check
Command: npx skills add https://github.com/babyworm/rtl-agent-team --skill rtl-lint-check

SYSTEM DOCUMENTATION & REQUIREMENTS

💡 This Skill includes scripts (resource) components.

What problem does it solve?

RTL projects often suffer from undetected lint issues across multiple tools, causing wasted debugging time and inconsistent quality. This skill runs Verilator, Verible, and slang to catch synthesizability, style, and semantic problems across rtl/ and sim/ with a unified report.

Core Features & Use Cases

Runs Verilator for synthesizability checks (latch, width, multi-driver issues)
Runs Verible for style and structure checks
Runs slang for semantic checks and port compatibility
Includes a project conventions checker to enforce coding rules
Use Case: before committing RTL changes to ensure clean lint across the pipeline

Quick Start

Run the lint workflow from the project root to execute the three tools and generate a merged report.

Frequently Asked Questions about rtl-lint-check

High-intent search queries and answers about installing and using this skill.

FAQPage Schema

How do I run Verilator, Verible, and slang together for RTL lint checks?▼

RTL lint checks run Verilator for synthesizability, Verible for style, and slang for semantics across rtl/ and sim/ directories, generating a merged report with a unified verdict. This catches latch, width, and multi-driver issues before committing changes.

What is the best way to enforce Verilog coding conventions across an entire project?▼

Verilog coding conventions are enforced by running a custom convention checker alongside Verilator, Verible, and slang. It identifies style, structure, and semantic violations across project directories, returning a unified verdict suitable for phase gates or pre-commit checks.

Does this RTL linting workflow support pre-commit hooks for individual files?▼

RTL linting supports pre-commit hooks and is applicable to both individual files and entire projects. It executes synthesizability, style, and semantic checks to provide a unified report, ensuring clean lint across the pipeline.

Why should I use multiple Verilog linters like Verilator and slang instead of just one?▼

Using multiple Verilog linters like Verilator and slang provides distinct checks: Verilator handles synthesizability, Verible covers style, and slang manages semantics and port compatibility. This combination prevents undetected lint issues and ensures consistent quality.

Can I check Verilog port compatibility and semantic rules automatically?▼

Verilog port compatibility and semantic rules are checked automatically using slang. When combined with Verilator and Verible during the lint workflow, it identifies semantic problems and port issues across rtl/ and sim/ directories.

What synthesizability issues can Verilator catch during RTL linting?▼

Verilator catches synthesizability issues like latch generation, width mismatches, and multi-driver problems during RTL linting. It runs alongside Verible and slang to provide a comprehensive unified report of all violations.