rtl-lint-check

RTL lint checks run Verilator for synthesizability, Verible for style, and slang for semantics across rtl/ and sim/ directories, generating a merged report with a unified verdict. This catches latch, width, and multi-driver issues before committing changes.

Verilog coding conventions are enforced by running a custom convention checker alongside Verilator, Verible, and slang. It identifies style, structure, and semantic violations across project directories, returning a unified verdict suitable for phase gates or pre-commit checks.

RTL linting supports pre-commit hooks and is applicable to both individual files and entire projects. It executes synthesizability, style, and semantic checks to provide a unified report, ensuring clean lint across the pipeline.

Using multiple Verilog linters like Verilator and slang provides distinct checks: Verilator handles synthesizability, Verible covers style, and slang manages semantics and port compatibility. This combination prevents undetected lint issues and ensures consistent quality.

Verilog port compatibility and semantic rules are checked automatically using slang. When combined with Verilator and Verible during the lint workflow, it identifies semantic problems and port issues across rtl/ and sim/ directories.

Verilator catches synthesizability issues like latch generation, width mismatches, and multi-driver problems during RTL linting. It runs alongside Verible and slang to provide a comprehensive unified report of all violations.