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verilog-lint

Lints and validates Verilog code with Verilator and Verible via temporary files.

1|Updated Apr 18, 2010
Search Tags:#rtl#verilator#hdl#verilog#verilog-lint#verible
One-click install
npx skills add https://github.com/morganp/dotfiles --skill verilog-lint
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: verilog-lint
Source: https://github.com/morganp/dotfiles/tree/main/config/claude/skills/verilog-lint
Command: npx skills add https://github.com/morganp/dotfiles --skill verilog-lint

SYSTEM DOCUMENTATION & REQUIREMENTS

What problem does it solve?

Lint and validate Verilog/SystemVerilog (RTL/HDL) code using Verilator and Verible. Trigger when Claude generates RTL, writes Verilog or SystemVerilog, checks HDL syntax, lints hardware description code, fixes Verilog errors, or when they mention modules, always blocks, wire/reg/logic declarations, clocks, resets, FSMs, synthesis, flip-flops, or any digital hardware design topic.

Core Features & Use Cases

  • Semantic linting with Verilator (--lint-only -Wall) to catch undeclared signals, width mismatches, undriven/unused nets, and blocking/non-blocking issues.
  • Style linting with Verible (verible-verilog-lint) to enforce naming conventions, whitespace, and port alignment.
  • End-to-end lint loop with up to 3 automatic iterations to produce a clean result, surfacing remaining issues with a diagnostic table if needed.

Quick Start

Provide the Verilog or SystemVerilog code you want linted and I will run Verilator and Verible to produce a clean RTL design.

Frequently Asked Questions about verilog-lint

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I lint Verilog RTL code to catch width mismatches and undriven nets?▼

To lint Verilog RTL, the skill uses Verilator with --lint-only -Wall to catch undeclared signals, width mismatches, undriven or unused nets, and blocking or non-blocking assignment issues. It writes code to a temporary file and reports semantic results.

Does Verible work with SystemVerilog for style and naming convention checks?▼

Verible works with SystemVerilog by running verible-verilog-lint to enforce style rules, naming conventions, whitespace, and port alignment. It is applied alongside Verilator to validate hardware description code.

What is the best way to automatically fix Verilog syntax errors during RTL design?▼

The best way to fix Verilog syntax errors is using the skill's end-to-end lint loop, which runs Verilator and Verible and automatically iterates up to three times to produce a clean RTL design, surfacing remaining issues in a diagnostic table.

Can I use this to check HDL always blocks, FSMs, and flip-flops before synthesis?▼

Yes, you can check HDL always blocks, FSMs, and flip-flops before synthesis. The skill triggers on digital hardware design topics and validates modules, wire or reg declarations, clocks, and resets.

Do I need to install Verilator and Verible to lint my SystemVerilog code?▼

Yes, you need Verilator and Verible installed to lint your SystemVerilog code. The skill requires both tools to execute semantic and style passes and write code to a temporary file for validation.

Why does my Verilog lint report show unused nets after running Verilator?▼

Your Verilog lint report shows unused nets because Verilator runs with -Wall to actively flag undriven and unused nets. If issues remain after three automatic iterations, the skill surfaces them in a diagnostic table.

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