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SystemVerilog RTL Design

Provide SystemVerilog RTL design patterns and templates for synthesizable hardware coding.

3|Updated Jan 5, 2026
Search Tags:#generate#design-patterns#rtl#fsm#cdc#systemverilog#synthesizable
One-click install
npx skills add https://github.com/codejunkie99/gateflow-cli --skill systemverilog-rtl-design
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: SystemVerilog RTL Design
Source: https://github.com/codejunkie99/gateflow-cli/tree/main/packages/claude-plugin/skills/sv-design
Command: npx skills add https://github.com/codejunkie99/gateflow-cli --skill systemverilog-rtl-design

SYSTEM DOCUMENTATION & REQUIREMENTS

What problem does it solve?

This skill provides ready-to-use SystemVerilog RTL design patterns, synthesis guidelines, and templates to standardize and accelerate hardware coding.

Core Features & Use Cases

  • Pattern Library: Reusable modules, FSM templates, parameterized designs, and common RTL blocks following modern SystemVerilog practices.
  • Synthesis Guidance: Clear guidelines for avoiding latches, using always_ff/always_comb, and reliable timing.
  • Real-World Scenarios: Use when prototyping modules, pipelines, CDCs, or when you need maintainable, synthesizable SV code.

Quick Start

Ask the Skill to provide a ready-to-use SystemVerilog RTL design snippet for a parameterized FIFO or FSM.

Frequently Asked Questions about SystemVerilog RTL Design

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I write a synthesizable SystemVerilog FSM using always_ff and always_comb?▼

To write a synthesizable SystemVerilog FSM, use always_ff for sequential state registers and always_comb for next-state logic. This skill provides FSM templates that enforce modern SV styles to ensure maintainable, latch-free hardware code.

What is the best way to parameterize SystemVerilog RTL modules for reusable design?▼

Parameterizing SystemVerilog RTL modules involves using parameters for bus widths and depths. This skill provides parameterized design templates and safe generate patterns to ensure your modules are reusable and synthesizable across different hardware configurations.

How do I handle clock-domain crossing in SystemVerilog RTL design?▼

Handle clock-domain crossing in SystemVerilog by using synchronizers and handshaking protocols. This skill offers CDC templates and synthesis guidelines to help you implement reliable RTL logic that avoids metastability issues across different clock domains.

Why does my SystemVerilog always_comb block generate latches during synthesis?▼

SystemVerilog always_comb blocks generate latches when signal assignments are incomplete in all conditional branches. This skill provides synthesis guidance and RTL design patterns to enforce complete assignments and avoid unintended latch generation.

Can I use SystemVerilog generate blocks for parameterized pipelines without causing synthesis errors?▼

Yes, you can use SystemVerilog generate blocks for parameterized pipelines by following safe generate patterns. This skill provides templates that ensure your generate constructs synthesize correctly while maintaining clean, scalable RTL code.

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