Avidlive
Community@codejunkie99
i dont like to code
Agent Skills by Avidlive
Showing 18 vetted skills indexed across 2 GitHub repositories.
codejunkie99SystemVerilog Verification
Apply SystemVerilog assertions, covergroups, and testbench templates to validate RTL designs.
codejunkie99SystemVerilog Development
Guide SystemVerilog RTL design with modern conventions and synthesizable patterns.
codejunkie99SystemVerilog RTL Design
Provide SystemVerilog RTL design patterns and templates for synthesizable hardware coding.
codejunkie99GateFlow Behavior
Automate SystemVerilog linting, simulation, and analysis task orchestration.
codejunkie99VCD Waveform Analysis
Parse VCD files to detect clocks and analyze signal timing.
codejunkie99SystemVerilog Lint Fixing
Fix SystemVerilog lint errors with predefined patch patterns.
codejunkie99SystemVerilog Testbench Patterns
Generate SystemVerilog testbench templates with clock, reset, and assertion patterns.
codejunkie99gf-sim
Automate SystemVerilog simulation with Verilator and emit GateFlow result blocks.
codejunkie99gf
Orchestrate SystemVerilog RTL development from planning through verification.
codejunkie99gf-expand
Resolve ambiguous GateFlow intents via clarifying questions and structured handoff payloads.
codejunkie99gf-plan
Generates comprehensive RTL implementation plans for hardware designs before coding.
codejunkie99gf-architect
Map SystemVerilog codebases to generate architecture documentation and module hierarchies.
codejunkie99tb-best-practices
Guide layered SystemVerilog testbench architecture with verification patterns.
codejunkie99gf-lint
Lint SystemVerilog code with Verilator and produce categorized warnings and errors.
codejunkie99gf-learn
Generate SystemVerilog exercises and review submitted solutions automatically.
codejunkie99gf-build
Orchestrate parallel SystemVerilog builds with phase-based decomposition and integration.
codejunkie99gf-router
Route user intents to GateFlow skills or agents with confidence scoring.
codejunkie99gf-summary
Analyze Verilator lint and simulation outputs into structured reports.