gf-architect

Map SystemVerilog codebases to generate architecture documentation and module hierarchies.

101|13|Updated Jan 28, 2026

Search Tags:#architecture #documentation #onboarding #analyze #module-hierarchy #SystemVerilog

Ready to run

npx skills add https://github.com/codejunkie99/Gateflow-Plugin --skill gf-architect

💬 Prompt for ChatGPT / Claude Chat▼

Please help me install this Agent Skill.
Skill: gf-architect
Source: https://github.com/codejunkie99/Gateflow-Plugin/tree/main/plugins/gateflow/skills/gf-architect
Command: npx skills add https://github.com/codejunkie99/Gateflow-Plugin --skill gf-architect

SYSTEM DOCUMENTATION & REQUIREMENTS

What problem does it solve?

This skill maps SystemVerilog codebases to produce architecture documentation and module hierarchies, enabling teams to understand complex RTL projects quickly without wading through scattered source files.

Core Features & Use Cases

Codebase mapping to generate a coherent architecture overview and per-module pages.
Onboarding support for new RTL projects by producing architecture reports and ownership guidance.
Use Case: a new project arrives; generate a CODEBASE.md-like map, module hierarchy, and a readable architecture document for review.

Quick Start

Use GateFlow to map a SystemVerilog project and generate architecture documentation.

Frequently Asked Questions about gf-architect

High-intent search queries and answers about installing and using this skill.

FAQPage Schema

How do I generate architecture documentation for a SystemVerilog codebase?▼

You can generate SystemVerilog architecture documentation by analyzing the codebase to map module hierarchies and produce structured architectural reports like CODEBASE.md without directly reading source files.

What is the best way to map a module hierarchy for RTL onboarding?▼

Mapping a module hierarchy for RTL onboarding involves analyzing the SystemVerilog project structure to output per-module details and a coherent architecture overview for new team members.

Can I analyze SystemVerilog code without directly reading source files?▼

Yes, you can analyze SystemVerilog code without directly reading source files by orchestrating subagents to map the codebase and return structured architectural documentation outputs.

Does this approach support generating per-module details for new RTL projects?▼

Yes, analyzing a new RTL project supports generating per-module details and a CODEBASE.md-like map to quickly produce a readable architecture document for review.

What are the limitations of mapping SystemVerilog codebases for maintenance?▼

Mapping SystemVerilog codebases for maintenance is limited to producing architectural reports and module hierarchies; it does not modify the source files or directly read them during analysis.