gf-architect

What problem does it solve?

This skill maps SystemVerilog codebases to produce architecture documentation and module hierarchies, enabling teams to understand complex RTL projects quickly without wading through scattered source files.

Core Features & Use Cases

• Codebase mapping to generate a coherent architecture overview and per-module pages.
• Onboarding support for new RTL projects by producing architecture reports and ownership guidance.
• Use Case: a new project arrives; generate a CODEBASE.md-like map, module hierarchy, and a readable architecture document for review.

Quick Start

Use GateFlow to map a SystemVerilog project and generate architecture documentation.