gf-architect

Name: gf-architect
Availability: InStock
Author: redclaus

Map SystemVerilog codebases and generate architecture documentation.

Updated Feb 13, 2026

Search Tags:#architecture #documentation #codebase analysis #rtl #systemverilog #hardware design

Ready to run

npx skills add https://github.com/RedClaus/cortex --skill gf-architect-redclaus

💬 Prompt for ChatGPT / Claude Chat▼

Please help me install this Agent Skill.
Skill: gf-architect
Source: https://github.com/RedClaus/cortex/tree/main/core/plugins/gateflow/skills/gf-architect
Command: npx skills add https://github.com/RedClaus/cortex --skill gf-architect-redclaus

SYSTEM DOCUMENTATION & REQUIREMENTS

💡 This Skill includes scripts (resource) and references (resource) components.

What problem does it solve?

This Skill automates the process of understanding, mapping, and documenting complex SystemVerilog codebases, significantly reducing the time and effort required for onboarding to new RTL projects or analyzing existing ones.

Core Features & Use Cases

Codebase Mapping: Generates a comprehensive map of modules, hierarchy, signals, and dependencies.
Architecture Documentation: Creates detailed documentation including hierarchy diagrams, signal flow, clock domains, and FSMs.
Use Case: When joining a new RTL project, use this Skill to quickly generate a visual map and documentation of the entire codebase, allowing you to understand module interactions and data flow within minutes.

Quick Start

Use the gf-architect skill to map the current SystemVerilog codebase.

Frequently Asked Questions about gf-architect

High-intent search queries and answers about installing and using this skill.

FAQPage Schema

How do I automatically generate architecture documentation for a SystemVerilog codebase?▼

To generate architecture documentation for a SystemVerilog codebase, this Skill orchestrates parallel subagents to parse files, extract structural information, and synthesize comprehensive documents detailing module hierarchy, signal flow, and clock domains.

What is the best way to map module hierarchy and signal flow in complex RTL projects?▼

Mapping module hierarchy and signal flow in complex RTL projects is best handled by automated codebase analysis tools that parse SystemVerilog files to extract structural dependencies and synthesize visual architecture documents.

Can I analyze large SystemVerilog files without running out of context or memory?▼

You can analyze large SystemVerilog files because this Skill employs chunked analysis and grep-first strategies, allowing it to process extensive codebases by breaking down files into manageable segments for structural extraction.

Does this codebase analysis tool support incremental updates for existing hardware design documentation?▼

Yes, this codebase analysis tool supports incremental updates, allowing you to quickly refresh existing hardware design architecture documents by re-parsing only modified SystemVerilog files instead of the entire project.

What specific structural information is extracted when documenting SystemVerilog codebases?▼

When documenting SystemVerilog codebases, the extracted structural information includes module hierarchy, signal flow, clock domains, finite state machines (FSMs), and module dependencies to create a comprehensive architecture map.