Map SystemVerilog codebases and generate architecture documentation.
npx skills add https://github.com/RedClaus/cortex --skill gf-architect-redclaus
Please help me install this Agent Skill. Skill: gf-architect Source: https://github.com/RedClaus/cortex/tree/main/core/plugins/gateflow/skills/gf-architect Command: npx skills add https://github.com/RedClaus/cortex --skill gf-architect-redclaus
This Skill automates the process of understanding, mapping, and documenting complex SystemVerilog codebases, significantly reducing the time and effort required for onboarding to new RTL projects or analyzing existing ones.
Use the gf-architect skill to map the current SystemVerilog codebase.
High-intent search queries and answers about installing and using this skill.
To generate architecture documentation for a SystemVerilog codebase, this Skill orchestrates parallel subagents to parse files, extract structural information, and synthesize comprehensive documents detailing module hierarchy, signal flow, and clock domains.
Mapping module hierarchy and signal flow in complex RTL projects is best handled by automated codebase analysis tools that parse SystemVerilog files to extract structural dependencies and synthesize visual architecture documents.
You can analyze large SystemVerilog files because this Skill employs chunked analysis and grep-first strategies, allowing it to process extensive codebases by breaking down files into manageable segments for structural extraction.
Yes, this codebase analysis tool supports incremental updates, allowing you to quickly refresh existing hardware design architecture documents by re-parsing only modified SystemVerilog files instead of the entire project.
When documenting SystemVerilog codebases, the extracted structural information includes module hierarchy, signal flow, clock domains, finite state machines (FSMs), and module dependencies to create a comprehensive architecture map.
AtaraxiaEpiphanyParse track-state.json files to aggregate task progress and detect blockers.
Dimen01Analyze hardware waveform traces and RTL source to diagnose simulation failures.
codejunkie99Provide SystemVerilog RTL design patterns and templates for synthesizable hardware coding.
zinohomeScan repository structure and generate ARCHITECTURE.md documentation with system overview and module relationships.
