Analyze hardware waveform traces and RTL source to diagnose simulation failures.
npx skills add https://github.com/Dimen01/skills --skill xwave
Please help me install this Agent Skill. Skill: xwave Source: https://github.com/Dimen01/skills/tree/main/skills/xwave Command: npx skills add https://github.com/Dimen01/skills --skill xwave
This skill addresses the complexity of debugging hardware simulation failures by providing a structured, evidence-based workflow for analyzing waveforms, bus protocols, and RTL signal behavior.
Use the xwave skill to load the waveform at path/to/simulation.fsdb and analyze the AXI bus signals for the suspected stall at the specified timestamp.
High-intent search queries and answers about installing and using this skill.
To debug an AXI bus hang in your hardware simulation waveform, you trace the valid and ready handshake signals to identify the stall timestamp, then correlate the behavior with the relevant RTL module to determine if the issue is a state machine deadlock or data hazard.
Correlating RTL source code with waveform anomalies involves connecting observed signal behavior symptoms directly to the emitted RTL or module hierarchy to identify root causes during hardware simulation failures.
Yes, you can diagnose APB protocol timeouts using structured waveform data by applying specialized playbooks to analyze bus handshake stalls and correlate them with the RTL hierarchy.
To identify the root cause of a state machine deadlock in an RTL simulation, you analyze the hardware waveform traces to trace signal behavior anomalies and verify state transitions against the RTL source code.
You do not strictly need RTL source roots to perform hardware waveform debugging, but providing them enables high-confidence root-cause analysis by correlating waveform symptoms directly with the source code.
trace1729Map VCD/FST waveform evidence to Chisel/Scala logic and RTL ownership.
kimasplundEliminate competing hypotheses through evidence-based reasoning in complex diagnostics.
EriemonGenerate and validate synthesizable Verilog-2001 RTL from hardware requirements.
babywormGenerate SVA assertions and simulation checks for AXI, AHB, and APB protocol violations.
