skills.rest
codejunkie99
codejunkie99COMMUNITY
Explore all skills by this author →
𝕏@Av1dliveGitHub

SystemVerilog Development

Guide SystemVerilog RTL design with modern conventions and synthesizable patterns.

3|Updated Jan 5, 2026
Search Tags:#verification#coding-standards#design-patterns#rtl#systemverilog#hdl#synthesizable
One-click install
npx skills add https://github.com/codejunkie99/gateflow-cli --skill systemverilog-development
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: SystemVerilog Development
Source: https://github.com/codejunkie99/gateflow-cli/tree/main/packages/claude-plugin/skills/systemverilog
Command: npx skills add https://github.com/codejunkie99/gateflow-cli --skill systemverilog-development

SYSTEM DOCUMENTATION & REQUIREMENTS

What problem does it solve?

This Skill helps hardware/software engineers write clean, synthesizable SystemVerilog RTL by applying modern conventions and safe coding patterns.

Core Features & Use Cases

  • Always block conventions: Use always_ff, always_comb, and appropriate reset patterns to improve reliability and synthesizability.
  • Signal types and widths: Use logic, typedefs, and explicit widths to avoid ambiguity.
  • FSM and handshaking patterns: Provide robust FSM templates and valid/ready handshakes.
  • Port declarations and RTL structure: ANSI-style, parameterized modules with clear interfaces.
  • Use Case: Imagine guiding an engineer to convert a dated RTL design into modern SV with clean state machines and robust resets.

Quick Start

Ask the system to generate a minimal 8-bit counter module in SystemVerilog using always_ff and a reset.

Frequently Asked Questions about SystemVerilog Development

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I write synthesizable SystemVerilog RTL using always_ff and always_comb?▼

To write synthesizable SystemVerilog RTL, use always_ff for sequential logic and always_comb for combinational logic, ensuring you apply explicit logic types and appropriate reset patterns for reliable hardware compilation.

What is the best way to design a finite state machine in SystemVerilog?▼

The best way to design a finite state machine in SystemVerilog is using robust FSM templates with explicit logic typedefs, parameterized modules, and clear valid/ready handshakes to ensure clean and reliable state transitions.

How do I convert legacy Verilog code to modern SystemVerilog conventions?▼

Converting legacy Verilog to modern SystemVerilog involves refactoring modules with ANSI-style port declarations, replacing wire/reg with explicit logic types, and applying safe coding patterns like always_ff for timing-critical components.

When should I use explicit widths and typedefs in SystemVerilog module interfaces?▼

You should use explicit widths and typedefs in SystemVerilog module interfaces whenever defining parameterized modules to avoid ambiguity, ensure synthesizability, and maintain clear structural interfaces across your RTL design.

Does SystemVerilog support valid/ready handshaking for timing-critical components?▼

Yes, SystemVerilog supports valid/ready handshaking for timing-critical components by utilizing robust FSM patterns and clear port declarations to safely coordinate data flow between synchronous modules.

Related Skills

Explore More Software Engineering Skills→
ArabelaTsoArabelaTso
142

rtl-specification-consistency-checker

Verify hardware specifications against Verilog, VHDL, or SystemVerilog RTL implementations.

Community
Advanced
ParadicatParadicat
1

fast-elaborator

Analyze Verilog/SystemVerilog RTL for gate count, logic depth, and flip-flop count using Yosys and OpenSTA.

Community
Intermediate
codejunkie99codejunkie99
3

SystemVerilog Verification

Apply SystemVerilog assertions, covergroups, and testbench templates to validate RTL designs.

Community
Intermediate
xsw632xsw632
2

workflow

Generate simulation-verified Verilog from plain English hardware descriptions.

Community
Advanced