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VCD Waveform Analysis

Parse VCD files to detect clocks and analyze signal timing.

3|Updated Jan 5, 2026
Search Tags:#analysis#timing#waveform#sv#vcd#clock-detection#signal-tracing
One-click install
npx skills add https://github.com/codejunkie99/gateflow-cli --skill vcd-waveform-analysis
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: VCD Waveform Analysis
Source: https://github.com/codejunkie99/gateflow-cli/tree/main/packages/claude-plugin/skills/sv-waveform
Command: npx skills add https://github.com/codejunkie99/gateflow-cli --skill vcd-waveform-analysis

SYSTEM DOCUMENTATION & REQUIREMENTS

What problem does it solve?

This skill helps engineers quickly analyze Value Change Dump (VCD) waveform files from SystemVerilog simulations, enabling faster clock detection, reset tracing, and signal timing diagnosis.

Core Features & Use Cases

  • VCD Parsing: Understands VCD structure and extracts signals, times, and values.
  • Clock Detection: Identifies clock nets and measures frequency and duty cycle.
  • Signal Tracing & Timing: Follows data through modules and analyzes setup/hold, delays, and propagation.
  • Anomaly & Debugging: Detects glitches, unknowns (X), and stuck signals for debugging verification failures.
  • Use Cases: Verify that your testbenches produce valid timing relationships across clocks and reset deassertion events in SV designs.

Quick Start

Run the sv-waveform analysis on your VCD file to extract clock, reset, and timing insights from the simulation trace.

Frequently Asked Questions about VCD Waveform Analysis

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I analyze VCD waveforms to extract clock and signal timing insights?▼

Analyze VCD waveforms by parsing the SystemVerilog simulation trace to identify clock nets, measure frequency and duty cycle, and trace signal propagation. This extracts timing relationships and detects glitches or unknown states across designs and testbenches.

What is the best way to detect clock frequency and duty cycle from a VCD file?▼

Detect clock frequency and duty cycle from a VCD file by applying clock detection logic to the parsed waveform data. This identifies clock nets and measures their toggling behavior to provide accurate timing metrics for verification.

Can I trace setup and hold violations using VCD parsing for SystemVerilog simulations?▼

Trace setup and hold violations in SystemVerilog simulations by parsing the VCD structure to follow data through modules. This analyzes signal delays and propagation to diagnose timing relationships across the verification environment.

Does VCD waveform analysis detect unknowns and glitches for debugging verification failures?▼

VCD waveform analysis detects unknowns and glitches by scanning the simulation trace for signal anomalies. It identifies stuck signals and X states, enabling targeted debugging of verification failures in SystemVerilog designs.

Can I analyze multiple VCD files simultaneously for cross-module timing verification?▼

Analyze multiple VCD files simultaneously by parsing each simulation trace to aggregate timing and signal integrity insights. This enables automated waveform analysis across various testbenches and verification environments.

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