Orchestrate SystemVerilog RTL development from planning through verification.
npx skills add https://github.com/codejunkie99/Gateflow-Plugin --skill gf
Please help me install this Agent Skill. Skill: gf Source: https://github.com/codejunkie99/Gateflow-Plugin/tree/main/plugins/gateflow/skills/gf Command: npx skills add https://github.com/codejunkie99/Gateflow-Plugin --skill gf
The gf skill eliminates the risk of delivering unverified code by coordinating planners, builders, and verifiers to produce working SystemVerilog RTL from natural-language requests.
Use the gf skill to plan and orchestrate a new SystemVerilog module from user requirements, then lint, simulate, and iterate until a working design is produced.
High-intent search queries and answers about installing and using this skill.
SystemVerilog development automation enforces a plan-first workflow that coordinates planning, code generation, linting, and simulation to deliver verified RTL from natural-language requirements.
Automating testbench generation and linting for SystemVerilog modules requires an orchestration workflow that integrates specialized agents to plan, build, verify, and iteratively debug the RTL.
Yes, you can build and verify SystemVerilog components concurrently by using an orchestrator agent that decomposes the overall RTL design into smaller modules for parallel implementation and verification.
Yes, automated SystemVerilog generation requires a planning step before coding to enforce structure and auditability, ensuring the planner agent defines the architecture before any code generation begins.
Iterative debugging during SystemVerilog simulation works by integrating lint and simulation steps that detect failures, then triggering refactor and debug agents to apply fixes until the RTL design is fully verified.
When your automated SystemVerilog lint and simulation workflow fails, the orchestration loop handles failures by providing structured status reports and invoking debug and refactor agents to apply iterative fixes.
MameMame777Write SystemVerilog Assertions as executable properties for RTL verification.
Dimen01Analyze hardware waveform traces and RTL source to diagnose simulation failures.
babywormEnforce analyze, fix, lint, testbench, and simulation verification for modified SystemVerilog files.
RedClausOrchestrate end-to-end SystemVerilog RTL development with planning, verification, and debugging agents.
