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assertion-design

Write SystemVerilog Assertions as executable properties for RTL verification.

Updated Jan 25, 2026
Search Tags:#assertions#bind#systemverilog#rtl-verification#formal-properties#verification-guidelines
One-click install
npx skills add https://github.com/MameMame777/FT4232Hmin --skill assertion-design
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: assertion-design
Source: https://github.com/MameMame777/FT4232Hmin/tree/main/.github/skills/assertion-design
Command: npx skills add https://github.com/MameMame777/FT4232Hmin --skill assertion-design

SYSTEM DOCUMENTATION & REQUIREMENTS

What problem does it solve?

SystemVerilog Assertions (SVAs) provide a formal, executable specification layer for RTL behavior, but teams often struggle to organize and reuse these properties while keeping them separate from the design. This skill advocates a specification-first approach, enabling precise, RTL-agnostic properties and a clean binding mechanism to DUTs.

Core Features & Use Cases

  • Specification-first design: write properties in SVAs that are RTL-agnostic and attach them via separate assertion modules (bind) rather than embedding in DUT.
  • Clear organization: dedicated locations for timing specs (sim/assertions/spec/), functional assertions (sim/assertions/functional/), and bindings (sim/assertions/bind/).
  • Scenarios: define timing requirements, protocol properties (e.g., AXI/UART), and formal properties for transaction sequences to guide rigorous verification.

Quick Start

  • Set up the directory structure as described above: sim/assertions/spec/, sim/assertions/functional/, sim/assertions/bind/.
  • Create sample files: sim/assertions/spec/uart_timing_spec.sva, sim/assertions/functional/Uart_Tx_Assertions.sv, and sim/assertions/bind/bind_Uart_Tx.sv; compile with ENABLE_ASSERTIONS and verify properties with a bound DUT.

Frequently Asked Questions about assertion-design

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I write SystemVerilog Assertions to keep RTL verification separate from the design code?▼

SystemVerilog Assertions (SVAs) can be kept separate by writing RTL-agnostic properties in standalone modules and attaching them to the DUT using bind statements. This enforces a clean separation of concerns for RTL verification.

What is the best way to organize formal properties and SVA files for protocol verification?▼

Organize formal properties and SVA files by separating them into dedicated directories for timing specifications (sim/assertions/spec/), functional assertions (sim/assertions/functional/), and bindings (sim/assertions/bind/) to guide rigorous protocol verification.

How do I bind assertion modules to a DUT for RTL verification?▼

To bind assertion modules for RTL verification, create RTL-agnostic SVA files, place binding statements in a dedicated bind directory (e.g., sim/assertions/bind/), and compile the design with an ENABLE_ASSERTIONS flag to verify properties with a bound DUT.

Can I use SystemVerilog Assertions to define timing requirements for interfaces like AXI or UART?▼

Yes, SystemVerilog Assertions can define executable timing specifications and protocol properties for interfaces like AXI or UART. They act as formal properties to verify transaction sequences and ensure interface compliance.

When should I use a specification-first approach with SVAs instead of embedding assertions in the DUT?▼

Use a specification-first approach with SVAs when you need to ensure reusability and keep formal properties RTL-agnostic. It prevents cluttering the DUT and allows precise enforcement of timing and functional properties via bind statements.

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