Mame
Community@mamemame777
1Followers
|28Public Repos
|8Published Skills
FPGA and Verification engineer.
Agent Skills by Mame
Showing 8 vetted skills indexed across 1 GitHub repositories.
MameMame777rtl-coding-standards
Enforce SystemVerilog RTL coding standards for timescale, declarations, resets, and naming.
Community
Basic
MameMame777python-debugging
Debug Python code systematically using exception traces, async patterns, and logging setups.
Community
Intermediate
MameMame777uvm-verification
Generate standardized UVM verification components for SystemVerilog testbenches.
Community
Basic
MameMame777mcp-workflow
Automate UVM testing workflows by orchestrating DSIM, FastMCP, and VS Code tasks.
Community
Advanced
MameMame777skill-creator
Generate, validate, and package Claude Skill Units with Python scripts.
Community
Intermediate
MameMame777assertion-design
Write SystemVerilog Assertions as executable properties for RTL verification.
Community
Advanced
MameMame777rtl-debugging
Guide engineers from verification failures to RTL root causes.
Community
Basic
MameMame777dsim-debugging
Diagnose DSIM compilation failures, runtime errors, and waveform issues.
Community
Advanced