Guide engineers from verification failures to RTL root causes.
npx skills add https://github.com/MameMame777/FT4232Hmin --skill rtl-debugging
Please help me install this Agent Skill. Skill: rtl-debugging Source: https://github.com/MameMame777/FT4232Hmin/tree/main/.github/skills/rtl-debugging Command: npx skills add https://github.com/MameMame777/FT4232Hmin --skill rtl-debugging
This Skill provides a structured methodology for debugging RTL designs, enabling engineers to identify and resolve failures in verification results, assertions, and scoreboards.
Run a failing RTL simulation, collect waveform data, assertion outputs, and scoreboard results, then apply the RTL-debugging workflow to identify the root cause and create a minimal reproducer to verify the fix.
High-intent search queries and answers about installing and using this skill.
To debug RTL failures, trace evidence from UVM scoreboards and waveforms to RTL signals, categorize issues into interface, datapath, or control domains, and infer root causes using hypothesis-driven experiments.
Finding the root cause of an RTL verification failure requires evidence-based tracing from test results to state machines, isolating the defect through assertion monitors, and generating minimal reproducers to validate the fix.
Create a minimal reproducer for an RTL bug by designing targeted stimuli based on waveform analysis and assertion-driven isolation, ensuring the reproducer accurately triggers the specific verification failure.
Yes, this RTL debugging workflow applies directly to simulation-driven verification across UVM-based testbenches, waveform analysis, and assertion monitors to triage causes and map evidence to RTL fixes.
Your RTL debugging process lacks traceability because it does not maintain structured debugging notes linking test evidence to RTL changes, which is required to enforce traceability from verification failures to fixes.
Triage RTL control and datapath issues by categorizing verification evidence from monitor outputs into interface, datapath, and control domains, then applying evidence-to-RTL mapping to infer the underlying root causes.
babywormGenerate minimal SystemVerilog testbenches and analyze VCD waveforms to isolate RTL failures.
adolfoaranaes12Reproduce bugs, identify root causes, and validate minimal fixes with the full test suite.
Dimen01Analyze hardware waveform traces and RTL source to diagnose simulation failures.
babywormEnforce analyze, fix, lint, testbench, and simulation verification for modified SystemVerilog files.
