skills.rest
babyworm
babywormCOMMUNITY
Explore all skills by this author →
WebsiteGitHub

rtl-p4s-bugfix

Enforce analyze, fix, lint, testbench, and simulation verification for modified SystemVerilog files.

43|9|Updated Feb 25, 2026
Search Tags:#verification#simulation#orchestrator#lint#bugfix#rtl#testbench
One-click install
npx skills add https://github.com/babyworm/rtl-agent-team --skill rtl-p4s-bugfix
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: rtl-p4s-bugfix
Source: https://github.com/babyworm/rtl-agent-team/tree/main/skills/rtl-p4s-bugfix
Command: npx skills add https://github.com/babyworm/rtl-agent-team --skill rtl-p4s-bugfix

SYSTEM DOCUMENTATION & REQUIREMENTS

What problem does it solve?

Prevents RTL fixes from being declared complete based solely on lint results by enforcing a full analyze → fix → lint → testbench → functional simulation verification cycle, ensuring functional correctness rather than just syntactic validity.

Core Features & Use Cases

  • End-to-end enforcement: Orchestrates analysis, code fixes, lint re-check, testbench creation or update, and functional simulation before marking fixes complete.
  • Integration with edit tracking: Hooks into PostToolUse:Edit to automatically detect modified .sv files and block session termination until verification passes.
  • Decision recording & policies: Produces decision records documenting root cause, fix rationale, and verification evidence and relies on a separate policy skill for checklists and escalation rules.
  • Use Cases: Fixing Phase 4 RTL bugs, regression verification after refactoring, integration bug fixes spanning multiple modules, and automated Phase 5→4 feedback loop remediation.

Quick Start

Invoke the rtl-p4s-bugfix orchestrator with a concise bug description to analyze the issue, apply fixes, update or generate testbenches, and run functional simulations to confirm the repair.

Frequently Asked Questions about rtl-p4s-bugfix

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I verify RTL bug fixes with functional simulation instead of just linting?▼

RTL bug fix verification requires an end-to-end cycle of analysis, code fixes, lint re-check, testbench updates, and functional simulation to confirm functional correctness rather than just syntactic validity. This prevents declaring fixes complete based solely on lint results.

What is the full verification cycle for SystemVerilog bug fixes?▼

The full SystemVerilog verification cycle enforces a sequential process: analyze the issue, apply fixes, run lint, generate or update testbenches, and execute functional simulation. It ensures functional correctness by requiring simulation success before allowing bug fix completion.

How do I automate testbench generation for modified SystemVerilog files?▼

Automated testbench generation for modified SystemVerilog files hooks into edit tracking to detect changes, then orchestrates testbench creation or updates and runs functional simulation. This blocks session termination until simulation verification passes.

Can I use RTL bug fix verification for regression and integration fixes?▼

RTL bug fix verification applies to Phase 4 bug fixes, regression verification after refactoring, integration bug fixes spanning multiple modules, and automated Phase 5 to Phase 4 feedback loop remediation where functional correctness must be demonstrated.

Why does RTL simulation fail to complete after fixing syntax errors?▼

Fixing syntax errors only satisfies lint checks, but RTL simulation requires functional correctness demonstrated through testbench execution. Without generating or updating testbenches and running functional simulation, the verification cycle remains incomplete and blocked.

Do I need a separate policy skill for RTL bug fix checklists and escalation rules?▼

Yes, the RTL bug fix orchestrator produces decision records documenting root cause and verification evidence, but it relies on a separate policy skill to provide checklists and escalation rules for the verification workflow.

Related Skills

Explore More Software Engineering Skills→
codejunkie99codejunkie99
3

SystemVerilog Testbench Patterns

Generate SystemVerilog testbench templates with clock, reset, and assertion patterns.

Community
Basic
BenWork17BenWork17

systematic-debugging

Guide four-phase debugging with root cause analysis and verification.

Community
Advanced
babywormbabyworm
43

systemverilog

Enforce SystemVerilog coding conventions on generated and modified RTL files.

Community
Advanced
babywormbabyworm
43

rtl-p4s-bugfix-policy

Enforce a four-step RTL bug-fix sequence with linting, testbench updates, and verification markers.

Community
Intermediate