skills.rest
MameMame777
MameMame777COMMUNITY
Explore all skills by this author →
𝕏@mame_edaedaGitHub

rtl-coding-standards

Enforce SystemVerilog RTL coding standards for timescale, declarations, resets, and naming.

Updated Jan 25, 2026
Search Tags:#coding-standards#naming-conventions#design-review#rtl#fpga#systemverilog#asic
One-click install
npx skills add https://github.com/MameMame777/FT4232Hmin --skill rtl-coding-standards
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: rtl-coding-standards
Source: https://github.com/MameMame777/FT4232Hmin/tree/main/.github/skills/rtl-coding-standards
Command: npx skills add https://github.com/MameMame777/FT4232Hmin --skill rtl-coding-standards

SYSTEM DOCUMENTATION & REQUIREMENTS

What problem does it solve?

This Skill codifies and enforces SystemVerilog RTL coding standards across projects to improve readability, reliability, and maintainability.

Core Features & Use Cases

  • Timescale Directive: Ensures every RTL file starts with a valid timescale.
  • Declaration Placement: Mandates declarations at the beginning of modules or blocks.
  • Consistent Reset & Always Blocks: Standardizes reset behavior and the correct always_ff/always_comb usage.
  • Naming & Style: Enforces consistent naming conventions for modules, signals, and interfaces.
  • Use Case: A design team adopts these standards to reduce review comments and speed up integration of RTL modules.

Quick Start

Apply the rtl-coding-standards to new RTL modules by aligning your module headers to the prescribed patterns and referencing the project docs for examples.

Frequently Asked Questions about rtl-coding-standards

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I enforce SystemVerilog RTL coding standards for FPGA and ASIC design?▼

To enforce SystemVerilog RTL coding standards, codify rules for timescale usage, declaration placement, and reset conventions across FPGA and ASIC projects to improve readability and reliability.

What are the best practices for naming conventions and reset behavior in SystemVerilog RTL modules?▼

Best practices for SystemVerilog RTL naming conventions and reset behavior involve standardizing always_ff and always_comb usage, ensuring consistent signal naming, and mandating declarations at the beginning of modules.

How do I validate module headers and state machines against existing project RTL templates?▼

Validate module headers and state machines by aligning new RTL modules to prescribed project patterns, leveraging existing templates to check interface definitions and ensure compliance with documented coding standards.

Does this RTL coding standards skill work with both FPGA and ASIC development workflows?▼

Yes, this RTL coding standards skill targets both FPGA and ASIC design teams, enforcing consistent always block types and timescale directives to speed up module integration across different hardware development workflows.

Why do I need a valid timescale directive at the start of every SystemVerilog RTL file?▼

A valid timescale directive is required at the start of every SystemVerilog RTL file to ensure consistent simulation timing and clock precision, preventing synthesis mismatches and maintaining reliability across the project.

How to standardize always_ff and always_comb usage to reduce design review comments?▼

Standardize always_ff and always_comb usage by enforcing strict reset conventions and declaration placement, ensuring clean production-grade SystemVerilog RTL that reduces design review feedback and speeds up integration.

Related Skills

Explore More Software Engineering Skills→
codejunkie99codejunkie99
3

SystemVerilog Verification

Apply SystemVerilog assertions, covergroups, and testbench templates to validate RTL designs.

Community
Intermediate
232322336666232322336666
4

remote-fm-formality

Verify RTL-to-gate equivalence on a remote Linux server with Synopsys Formality.

Community
Advanced
yonatangrossyonatangross
217

commit

Create Git commits following the Conventional Commits specification with local validation.

Community
Intermediate
YuunqiLiuYuunqiLiu
1

rtl-coding-style

Enforces consistent formatting and naming standards for RTL designs.

Community
Advanced