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remote-fm-formality

Verify RTL-to-gate equivalence on a remote Linux server with Synopsys Formality.

4|4|Updated Apr 8, 2026
Search Tags:#formal-verification#remote-server#rtl#gate-netlist#svf#eda-tools
One-click install
npx skills add https://github.com/232322336666/vibe_circuit_deisgn.skill --skill remote-fm-formality
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: remote-fm-formality
Source: https://github.com/232322336666/vibe_circuit_deisgn.skill/tree/main/remote-fm-formality
Command: npx skills add https://github.com/232322336666/vibe_circuit_deisgn.skill --skill remote-fm-formality

SYSTEM DOCUMENTATION & REQUIREMENTS

What problem does it solve?

Formal verification of RTL-to-gate equivalence on a remote Linux server using Synopsys Formality, ensuring gate-level netlists match the original RTL with SVF guidance from DC.

Core Features & Use Cases

  • Remote RTL-vs-gate formal verification using Synopsys Formality.
  • Copy-from-template workflow to ensure correct setup and TOP_DESIGN_NAME configuration.
  • End-to-end flow from environment setup to result analysis and reporting on a remote server.

Quick Start

Copy from the verified example template, configure TOP_DESIGN_NAME in the setup, and run the FM verification workflow on the remote server.

Frequently Asked Questions about remote-fm-formality

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I perform RTL-to-gate equivalence verification using Synopsys Formality on a remote Linux server?▼

This Skill performs RTL-to-gate equivalence verification on a remote Linux server using Synopsys Formality, applying SVF files from DC synthesis to verify gate-level netlists against original RTL sources.

What files do I need for SVF-guided formal verification of gate-level netlists?▼

SVF-guided formal verification requires Synopsys Formality license, SVF files generated by DC synthesis, gate-level netlists, original RTL sources, and remote server access to execute the equivalence check.

When should I run RTL-vs-gate formal verification after synthesis?▼

RTL-vs-gate formal verification should be run after DC synthesis and SVF generation to ensure the gate-level netlist functionally matches the original RTL design before proceeding to layout.

Can I verify RTL against gate-level netlists on a remote server without local EDA tools?▼

Yes, you can verify RTL against gate-level netlists on a remote server by connecting to the remote Linux machine where Synopsys Formality is installed, applying template-based setup and SVF-guided checks remotely.

What is the best way to set up Formality checks for a new gate-level netlist?▼

The best way to set up Formality checks is using the copy-from-template workflow to ensure correct environment setup and TOP_DESIGN_NAME configuration before executing the remote verification flow.

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