Orchestrate end-to-end SystemVerilog RTL development with planning, verification, and debugging agents.
npx skills add https://github.com/RedClaus/cortex --skill gf-redclaus
Please help me install this Agent Skill. Skill: gf Source: https://github.com/RedClaus/cortex/tree/main/core/plugins/gateflow/skills/gf Command: npx skills add https://github.com/RedClaus/cortex --skill gf-redclaus
This Skill automates the entire SystemVerilog development lifecycle, from initial planning and code generation to verification and debugging, ensuring working RTL code is delivered efficiently.
Use the gf skill to create a FIFO with a valid/ready interface and a self-checking testbench.
High-intent search queries and answers about installing and using this skill.
You can automate SystemVerilog RTL design and verification by orchestrating an end-to-end workflow that handles planning, code generation, simulation, and debugging in a structured iterative loop.
The best way to debug SystemVerilog code is using an agent-driven workflow that integrates linting and simulation, automatically identifying and resolving issues within an iterative verification loop.
Yes, you can generate a FIFO with a valid ready interface and a self-checking testbench by requesting the module, which triggers automated planning, RTL creation, and rigorous verification.
Yes, this approach supports complex hardware components by first planning the architecture, then building individual modules in parallel, and finally verifying each component rigorously.
To implement and verify a UART controller using SystemVerilog, an automated orchestrator triggers planning, generates RTL code, runs simulations, and debugs failures to deliver a verified module.
Automating the entire RTL development lifecycle requires a structured, iterative loop for verification and debugging, meaning complex designs may need multiple iterations to pass simulation and linting checks.
czh-ee-2023Convert Zotero paper hardware descriptions into synthesizable SystemVerilog RTL code.
ArabelaTsoVerify hardware specifications against Verilog, VHDL, or SystemVerilog RTL implementations.
Dimen01Analyze hardware waveform traces and RTL source to diagnose simulation failures.
babywormRun UVM-based verification on RTL with commercial simulators and merge coverage artifacts.
