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rtl-coding-style

Enforce RTL coding style for Verilog and SystemVerilog code.

1|1|Updated Jun 15, 2023
Search Tags:#code review#coding style#rtl#systemverilog#verilog#hardware design
One-click install
npx skills add https://github.com/Paradicat/demo --skill rtl-coding-style
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: rtl-coding-style
Source: https://github.com/Paradicat/demo/tree/main/agent_pack/skills/rtl-coding-style
Command: npx skills add https://github.com/Paradicat/demo --skill rtl-coding-style

SYSTEM DOCUMENTATION & REQUIREMENTS

💡 This Skill includes references (resource) components.

What problem does it solve?

This Skill provides a comprehensive guide to writing clean, maintainable, and synthesizable Verilog/SystemVerilog RTL code, ensuring consistency and reducing bugs in hardware designs.

Core Features & Use Cases

  • Coding Standards: Enforces best practices for indentation, naming, module structure, and parameter usage.
  • Code Review Aid: Serves as a reference for reviewing RTL code for adherence to style guidelines.
  • Code Generation: Guides the generation of new RTL code that follows established conventions.
  • Use Case: When generating a new Verilog module for a digital design, use this Skill to ensure the code is well-formatted, variables are named clearly, and parameters are used effectively.

Quick Start

Apply the RTL coding style guide to the provided Verilog code snippet.

Frequently Asked Questions about rtl-coding-style

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
What is the best way to enforce a consistent RTL coding style for Verilog and SystemVerilog?▼

The best way to enforce a consistent RTL coding style is to apply a strict guide covering indentation, naming conventions, and module definitions. This ensures Verilog and SystemVerilog code remains clean, maintainable, and synthesizable.

How do I structure SystemVerilog modules to ensure they are synthesizable and maintainable?▼

To structure synthesizable SystemVerilog modules, follow established conventions for module definitions, parameter usage, and sequential/combinational logic separation. This practice reduces bugs and ensures clarity in digital design projects.

Can I use a coding style reference to review existing Verilog code?▼

Yes, you can use an RTL coding style reference to review existing Verilog code. It serves as an aid to check adherence to style guidelines, ensuring proper indentation, naming conventions, and parameter usage.

Does following an RTL coding guide help with generating new SystemVerilog code?▼

Following an RTL coding guide directly helps generate new SystemVerilog code by providing a framework for well-formatted output. It ensures variables are named clearly and parameters are used effectively from the start.

Why does my SystemVerilog code fail synthesis due to poor sequential and combinational logic separation?▼

SystemVerilog code may fail synthesis if sequential and combinational logic are poorly separated. Enforcing strict RTL coding standards addresses this by guiding proper logic definition, ensuring the hardware description is synthesizable.

What naming conventions should I use for digital design parameters in Verilog?▼

For Verilog digital design parameters, use clear and consistent naming conventions defined by an RTL style guide. This ensures parameters are used effectively, improving overall code clarity and maintainability.

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