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rtl-p5s-cdc-policy

Generate CDC verification policies, SDC constraint patterns, and synchronizer guidance for RTL designs.

43|9|Updated Feb 25, 2026
Search Tags:#verification#coding-conventions#rtl#cdc#sdc#clock-domain-crossing#synchronizer
One-click install
npx skills add https://github.com/babyworm/rtl-agent-team --skill rtl-p5s-cdc-policy
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: rtl-p5s-cdc-policy
Source: https://github.com/babyworm/rtl-agent-team/tree/main/skills/rtl-p5s-cdc-policy
Command: npx skills add https://github.com/babyworm/rtl-agent-team --skill rtl-p5s-cdc-policy

SYSTEM DOCUMENTATION & REQUIREMENTS

What problem does it solve?

Provides a concise, actionable CDC verification policy for RTL projects so engineers can consistently identify clock domain crossings, apply naming conventions, and choose appropriate synchronizers without modifying RTL.

Core Features & Use Cases

  • Naming convention enforcement: Defines required clock and reset port names and flags convention violations for early remediation.
  • Synchronizer selection guidance: Recommends synchronizer patterns for single-bit control, multi-bit buses, counters, pulses, and SRAM boundaries.
  • SDC & checklist generation: Supplies SDC constraint patterns, violation classifications, and a final CDC checklist to produce consistent reports for sign-off.
  • Use Case: During CDC review of an SoC RTL drop, use the policy to map domains, classify crossings, generate cdc_constraints.sdc, and recommend synchronizer implementations.

Quick Start

Ask the skill to audit RTL for clock/reset naming and cross-domain paths, list violations, and recommend synchronizer types and SDC constraint patterns.

Frequently Asked Questions about rtl-p5s-cdc-policy

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I enforce CDC naming conventions in RTL without modifying the source code?▼

CDC naming conventions are enforced by checking clock and reset port names against policy rules, flagging violations for early remediation while preserving RTL unchanged.

What is the best way to select synchronizers for multi-bit bus clock domain crossings?▼

Synchronizer selection is guided by classifying crossing types, recommending specific patterns for single-bit control, multi-bit buses, counters, and SRAM boundaries.

How do I generate SDC constraints for clock domain crossing analysis in an ASIC workflow?▼

Generate SDC constraints by applying CDC policy templates to mapped domains, producing constraint patterns and violation classifications for sign-off reports.

Can I use this CDC policy with both formal and structural verification tools?▼

Yes, the CDC policy provides compatible guidance for both structural and formal CDC tools, ensuring consistent domain mapping and violation classification across workflows.

How do I create a CDC sign-off checklist for an SoC RTL drop?▼

Create a CDC sign-off checklist by auditing cross-domain paths, listing naming violations, applying synchronizer recommendations, and generating final verification reports.

Why do I need SDC constraint templates for FPGA clock domain crossing verification?▼

SDC constraint templates are needed to consistently classify crossings and provide structured patterns that ensure reliable verification across ASIC and FPGA designs.

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