skills.rest
hw-native-sys
hw-native-sysOFFICIAL
Explore all skills by this author →
GitHub

ascendc-npu-arch

Map Ascend NPU architectures, generations, and SocVersion references.

11|51|Updated Mar 10, 2026
Search Tags:#fp8#ascend-npu#npu-architecture#arch35#regbase#simt
One-click install
npx skills add https://github.com/hw-native-sys/pypto-lib --skill ascendc-npu-arch
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: ascendc-npu-arch
Source: https://github.com/hw-native-sys/pypto-lib/tree/main/.claude/skills/cannbot-skills/ascendc-npu-arch
Command: npx skills add https://github.com/hw-native-sys/pypto-lib --skill ascendc-npu-arch

SYSTEM DOCUMENTATION & REQUIREMENTS

💡 This Skill includes references (resource) components.

What problem does it solve?

Provide quick, structured information on Ascend NPU architectures, generations, and arch35 optimizations to aid architecture-aware development.

Core Features & Use Cases

  • Architecture generation mapping, NpuArch and SocVersion references
  • arch35 optimizations such as Regbase, SIMT, and FP8 guidance
  • Use cases for architecture-informed conditional compilation and performance tuning

Quick Start

Consult the references in this knowledge base to quickly understand Ascend NPU architectures and arch35 optimizations.

Frequently Asked Questions about ascendc-npu-arch

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I map Ascend NPU architectures to specific SocVersion identifiers for compile-time decisions?▼

To map Ascend NPU architectures to SocVersion identifiers, consult the structured references providing NpuArch and generation mappings to inform architecture-aware conditional compilation and performance tuning.

What is arch35 and how does it optimize Ascend NPU performance?▼

arch35 is an Ascend NPU architecture generation that supports specific performance optimizations including Regbase, SIMT, and FP8 guidance for precise development and compile-time tuning decisions.

How do I use FP8 and Regbase details for Ascend NPU architecture-informed development?▼

You use FP8 and Regbase details by referencing linked materials in the knowledge hub to apply arch35-specific optimizations for architecture-informed conditional compilation and performance tuning.

Does the Ascend NPU architecture knowledge hub support arch35-specific SIMT optimizations?▼

Yes, the Ascend NPU architecture knowledge hub supports arch35-specific SIMT optimizations by articulating architecture relationships and providing linked references for Regbase and FP8 details.

What are the limitations of using arch35 optimizations for Ascend NPU development?▼

The knowledge hub provides arch35 optimization references for Ascend NPU development, but limitations depend on specific chip characteristics and SocVersion mappings required for your compile-time decisions.

Related Skills

Explore More Software Engineering Skills→
jackspacejackspace
16

torchdrug

Apply graph neural networks to drug discovery tasks with PyTorch.

Community
Advanced
mindspore-aimindspore-ai
258

triton-ascend-example-matmul

Demonstrate Triton Ascend matmul with 2D tiling and K-loop accumulation.

Official
Advanced
CantaraCantara
3

Samsung Electro-Mechanics Part Number Reference

Decode Samsung Electro-Mechanics part numbers for MLCCs, resistors, and inductors.

Official
Basic
z4nr34lz4nr34l

supabase-postgres-best-practices

Enforce Supabase Postgres performance best practices across eight priority categories.

Community
Advanced