hw-native-sys
Official@hw-native-sys
Specialized engineering suite for Ascend NPU kernel development, PTOAS compiler maintenance, and high-performance C++ operator validation.
Agent Skills by hw-native-sys
Showing 48 vetted skills indexed across 4 GitHub repositories.
ptoas-npu-validation-a5
Build and execute PTOAS A5 kernel validation workflows on NPU or simulator.
ptoas-test-framework-guidance
Place PTOAS tests in lit, VPTO, or TileLang ST frameworks with validation commands.
build-ptoas-wsl
Build and validate the PTOAS compiler toolchain from source in WSL.
ptoas-project-development
Coordinate PTOAS compiler changes across MLIR ODS, C++, CLI, Python, docs, and tests.
pto-isa-cpu-sim-kernel-test
Validate PTOAS-generated PTO kernels against the local PTO ISA CPU simulator.
generate-vpto-release-doc
Regenerate bundled PTO ISA reference documentation from distributed specification and instruction chapter files.
ptoas-publish-pr
Publish scoped PTOAS changes as a draft GitHub pull request.
debug-matmul-mx
Diagnose MX and cube matmul failures across shapes, layouts, and writeback.
pto-gym-vpto-validation
Validate PTO-Gym cases using the PTOAS VPTO backend with A5 flags.
camodel-isa-verification
Verify PTO-ISA instruction behavior and output correctness via CA model simulator tests and log analysis.
ptoas-manual-authoring
Writes user-facing PTOAS manuals and ISA specification documents without exposing implementation details.
ptoas-build-and-abs
Rebuilds the PTOAS compiler and compiles the Abs sample to generate VPTO output.
resolve-dsl-issue
Reproduce and resolve DSL compilation failures from GitHub issues using PTOAS logs.
rewrite-kernel-with-vmi
Rewrite AscendC or CCE kernels into PTODSL implementations preserving ABI and synchronization.
llvm-test-tool-fallback
Locate missing lit or FileCheck tools in LLVM environments.
msprof-op-simulator-insight
Profile PTOAS-generated kernels and export simulator data for MindStudio Insight.
ptodsl-tilelib-template-authoring
Author and debug PTODSL TileLib templates while preserving metadata and runtime semantics.
benchmark
Benchmark Ascend hardware runtime performance across host and device timings.
insight-trace
Generate MindStudio Insight traces for kernel_entry kernels via msprof op simulator.
onboard-arch-precheck
Detect host Ascend silicon and block mismatched onboard test invocations.
checkout-pr
Configure git remotes and check out local PR work branches.
review-pr
Analyze merge-base diffs to verify PR changes align with stated goals.
multi-repo-setup
Clones or updates external repos into a build directory for CI parity.
clean-branches
Remove local and fork branches merged into main, including squash merges.
Frequently Asked Questions About hw-native-sys
FAQPage SchemaWhat specific tasks can engineers perform with these capabilities?▼
Engineers can design, debug, and validate Ascend C kernels, perform NPU architecture mapping, execute PTOAS compiler transformations, and generate ISA reference documentation. The suite supports end-to-end operator development, from tiling strategy design to numerical precision debugging and kernel launch verification.
Which technical personas benefit from this registry?▼
This registry is designed for NPU firmware engineers, compiler developers, and performance optimization specialists working on Ascend hardware. It provides targeted support for those managing complex C++ operator lifecycles, hardware-specific ISA verification, and large-scale compiler project maintenance.
What are the primary hardware and software prerequisites?▼
Successful operation requires a configured Ascend NPU environment, the CANN software stack, and a compatible Linux build environment such as WSL. Users must ensure proper installation of the MindStudio Insight simulator and the PTOAS compiler toolchain to enable kernel profiling and ISA simulation.