debug-matmul-mx

Diagnose MX and cube matmul failures across shapes, layouts, and writeback.

30|74|Updated Jan 29, 2026
One-click install
npx skills add https://github.com/hw-native-sys/PTOAS --skill debug-matmul-mx
Or copy as Structured Prompt for Agent
Please help me install this Agent Skill.
Skill: debug-matmul-mx
Source: https://github.com/hw-native-sys/PTOAS/tree/main/.codex/skills/debug-matmul-mx
Command: npx skills add https://github.com/hw-native-sys/PTOAS --skill debug-matmul-mx

SYSTEM DOCUMENTATION & REQUIREMENTS

What problem does it solve?

This Skill diagnoses and resolves MX and cube matmul failures caused by shape mismatches, fractal layout errors, wrapper lowering defects, scale packing issues, FP4 byte staging, writeback bugs, or simulator behavior.

Core Features & Use Cases

  • Layered Debugging: Separates logical shapes, physical layouts, MTE transfers, wrapper expansion, emitter control packing, cube computation, and output writeback.
  • Targeted Isolation: Uses all-ones checks, patterned data, independent data and scale tests, and simulator middle-layer logs to localize failures.
  • Framework-Aware Analysis: Compares handwritten VPTO cases with TileLang and PTODSL authoring IR, expanded operations, and final hardware controls.
  • Use Case: Apply this Skill when an A5 FP8 or FP4 matmul case produces incorrect output, especially when logical and physical K dimensions differ or padded packed-byte buffers are involved.

Quick Start

Use the debug-matmul-mx skill to investigate the failing MX matmul case, synchronize its kernel, host, and golden shapes, and identify the first incorrect execution layer.

Frequently Asked Questions about debug-matmul-mx

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I debug incorrect output in an A5 FP4 or FP8 matmul workload?

To debug incorrect A5 FP4 or FP8 matmul output, synchronize kernel, host, and golden shapes, then isolate failures layer by layer using all-ones checks and simulator log correlation to find the first incorrect execution layer.

Why does my handwritten VPTO micro-op produce wrong matmul results in the simulator?

Handwritten VPTO micro-op matmul failures often stem from physical byte-layout validation errors or wrapper lowering defects; isolate data and scale patterns independently and inspect expanded operations against simulator middle-layer logs to localize the issue.

How do I resolve fractal layout and scale packing errors in TileLang generated matmul cases?

Resolve TileLang matmul fractal layout and scale packing errors by separating logical shapes from physical layouts, inspecting the authoring IR, and validating padded packed-byte buffers and physical byte layouts against expected controls.

What is the best way to isolate shape mismatches when logical and physical K dimensions differ in MX matmul?

The best way to isolate MX matmul shape mismatches when logical and physical K dimensions differ is performing systematic shape synchronization across kernel, host, and golden arrays, followed by targeted all-ones sanity checks.

Can I use this debugging approach for both simulator environments and validation environments?

Yes, this debugging approach applies to handwritten VPTO micro-ops and TileLang or PTODSL generated cases running in both simulators and validation environments, covering MTE transfers, emitter control packing, and output writeback.

When should I check wrapper lowering and emission controls during cube matmul debugging?

Check wrapper lowering and emission controls during cube matmul debugging when initial shape synchronization passes but computation fails, using IR inspection to compare expanded operations with final hardware controls.