boot-debug-expert

Diagnose ARM SoC boot failures via power sequencing and PLL lock analysis.

4|2|Updated Mar 14, 2026

Search Tags:#debug #hardware #boot #bsp #pll #arm soc #power sequencing

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npx skills add https://github.com/jonaschen/ai-bsp-knowledge-skill-sets --skill boot-debug-expert

💬 Prompt for ChatGPT / Claude Chat▼

Please help me install this Agent Skill.
Skill: boot-debug-expert
Source: https://github.com/jonaschen/ai-bsp-knowledge-skill-sets/tree/main/skills/boot-debug-expert
Command: npx skills add https://github.com/jonaschen/ai-bsp-knowledge-skill-sets --skill boot-debug-expert

SYSTEM DOCUMENTATION & REQUIREMENTS

💡 This Skill includes scripts (resource) and references (resource) components.

What problem does it solve?

This Skill helps engineers diagnose and resolve critical hardware boot and bring-up failures on ARM SoC platforms, preventing common mistakes and accelerating debugging.

Core Features & Use Cases

Power Sequencing Analysis: Identifies issues with the order and timing of power rail activation.
PLL Lock Debugging: Helps troubleshoot failures in Phase-Locked Loop synchronization, crucial for clock stability.
CoreSight/ADIv6 Integration: Assists in debugging issues related to ARM's CoreSight debug and trace architecture.
Use Case: When a new board fails to boot past the initial power-on sequence, this Skill guides you through checking PMIC logs, PLL lock status, and isolation cell configurations to pinpoint the root cause.

Quick Start

Use the boot-debug-expert skill to analyze a PMIC log file located at /path/to/pmic.log to identify power sequencing violations.

Frequently Asked Questions about boot-debug-expert

High-intent search queries and answers about installing and using this skill.

FAQPage Schema

How do I debug ARM SoC boot failures caused by power sequencing issues?▼

To debug ARM SoC power sequencing boot failures, you need to analyze PMIC logs to identify violations in the order and timing of voltage rail activation. This diagnostic process checks power island states to pinpoint the root cause of early-stage bring-up failures.

Why does my ARM hardware fail to boot past the initial power-on sequence?▼

Hardware boot failures during initial power-on often stem from incorrect voltage rail activation, PLL lock failures, or misconfigured isolation cells. Analyzing PMIC logs and clock domains helps identify whether the issue originates in power sequencing or Phase-Locked Loop synchronization.

How do I troubleshoot PLL lock issues during hardware bring-up?▼

Troubleshooting PLL lock issues during hardware bring-up requires analyzing clock domains and Phase-Locked Loop synchronization status. By examining CoreSight debug data and power island states, you can determine if clock instability is preventing the ARM SoC from booting.

What do I need to diagnose early-stage hardware boot failures on ARM platforms?▼

Diagnosing early-stage hardware boot failures on ARM platforms requires understanding of voltage rails, clock domains, and isolation cells. You need access to PMIC log files and knowledge of ADIv6 CoreSight architecture to effectively perform root-cause analysis.

Can I use CoreSight and ADIv6 to debug ARM SoC power-on failures?▼

Yes, CoreSight and ADIv6 are integral to debugging ARM SoC power-on failures. The architecture assists in tracing and debugging issues related to early-stage boot sequences, allowing you to analyze isolation cell configurations and power island states.

What is the best way to analyze PMIC logs for power sequencing violations?▼

The best way to analyze PMIC logs for power sequencing violations is through a guided diagnostic process that examines voltage rail activation timing. By using Socratic questioning, the analysis isolates specific power island states and clock domain failures.