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circuit-fibsqrt

Designs digital logic circuits for Fibonacci of integer square root functions.

Updated Feb 24, 2026
Search Tags:#sequential logic#circuit design#digital logic#HDL#FPGA#combinational logic
One-click install
npx skills add https://github.com/Zurybr/lefarma-skills --skill circuit-fibsqrt-zurybr
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: circuit-fibsqrt
Source: https://github.com/Zurybr/lefarma-skills/tree/main/letta/benchmarks/trajectory-only/circuit-fibsqrt
Command: npx skills add https://github.com/Zurybr/lefarma-skills --skill circuit-fibsqrt-zurybr

SYSTEM DOCUMENTATION & REQUIREMENTS

💡 This Skill includes references (resource) components.

What problem does it solve?

This Skill provides guidance for designing and implementing digital logic circuits that compute composite mathematical functions, such as fib(isqrt(N)), under resource constraints.

Core Features & Use Cases

  • Algorithm Decomposition: Breaks down complex functions into combinational and sequential components.
  • Resource Estimation: Helps estimate gate counts and simulation steps before implementation.
  • Verification Strategies: Outlines methods for component-level and integration testing.
  • Use Case: Implementing a circuit that calculates the Fibonacci number of the integer square root of an input N within a gate-level simulator.

Quick Start

Use the circuit-fibsqrt skill to design a combinational logic circuit for integer square root calculation.

Frequently Asked Questions about circuit-fibsqrt

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I design digital logic circuits for composite math functions like Fibonacci of integer square root?▼

Designing digital logic for composite math requires decomposing functions into combinational and sequential logic components for gate-level simulation. This Skill guides algorithm decomposition, resource estimation, and verification strategies for circuits like fib(isqrt(N)).

What is the best way to estimate resource constraints for FPGA circuit synthesis?▼

Estimating resource constraints involves analyzing gate counts and simulation steps before implementing your HDL logic design. This Skill helps calculate hardware requirements for complex mathematical circuits to ensure they operate within resource limits.

Can I implement sequential and combinational logic together in a gate-level simulator?▼

You can implement sequential and combinational logic together by applying algorithm decomposition to separate state elements from combinational paths. This Skill outlines integration testing methods for verifying composite functional circuits in gate-level simulators.

How do I verify an HDL-style logic circuit that calculates integer square root?▼

Verifying HDL-style logic circuit implementation requires structured component-level and integration testing methods. This Skill outlines verification strategies for testing mathematical circuits like integer square root and Fibonacci calculations.

What are the limitations of designing complex mathematical circuits under strict resource constraints?▼

Designing complex mathematical circuits under resource constraints requires balancing combinational logic depth and sequential clock cycles. This Skill helps estimate gate counts and simulation steps to identify limitations before implementing composite functions.

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