circuit-fibsqrt

Gate-level circuits for isqrt use iterative algorithms implemented with primitive gates (AND, OR, XOR, NOT, MUX) and arithmetic blocks like comparators and subtractors. Build multi-bit ripple-carry adders and comparators first, then combine them into a sequential logic structure that refines the result over iterations, tracking intermediate values through named signals in a text-based netlist.

Fibonacci circuits use sequential logic with storage elements and arithmetic building blocks to generate sequences. Implement half adders and full adders as components, then chain them with feedback loops in a text-based gate netlist to accumulate successive Fibonacci values, optimizing for gate count while preserving intermediate signal names for tracing.

Text-based gate netlists specify primitive gates (AND, OR, XOR, NOT, MUX) and their connections with consistent signal naming. Start with simple 1-bit adders, verify multi-bit expansion, then compose larger arithmetic blocks like N-bit adders and comparators into event-driven simulators that compute math functions under resource constraints.

Event-driven simulators support feedback loops for sequential computation. Text-based gate netlists with named signals and primitive gate definitions enable simulation of iterative algorithms; verify behavior by paper-tracing signal states and testing against known outputs for math functions like isqrt and Fibonacci.

Core blocks include half adders, full adders, N-bit ripple-carry adders, subtractors, and comparators built from primitive gates. These components form the foundation for larger circuits computing math functions; they're specified in text netlists and optimized by minimizing gate count while maintaining correct signal propagation.