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ila-hw-debug

Insert Integrated Logic Analyzers and execute hardware debug cycles on FPGA silicon.

11|7|Updated Jun 5, 2026
Search Tags:#debug#hardware#fpga#waveform#vivado#jtag#ila
One-click install
npx skills add https://github.com/LNC0831/oh-my-fpga --skill ila-hw-debug
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: ila-hw-debug
Source: https://github.com/LNC0831/oh-my-fpga/tree/main/skills/ila-hw-debug
Command: npx skills add https://github.com/LNC0831/oh-my-fpga --skill ila-hw-debug

SYSTEM DOCUMENTATION & REQUIREMENTS

What problem does it solve?

This skill solves the challenge of debugging complex, non-deterministic behavior on physical FPGA hardware that cannot be replicated or observed in a simulation environment.

Core Features & Use Cases

  • Integrated Logic Analyzer (ILA) Orchestration: Automates the insertion, configuration, and connection of debug cores into your FPGA design.
  • Hardware Capture Loop: Manages the full cycle of programming the device, setting precise trigger conditions, and reading back waveform data for analysis.
  • Use Case: Use this when your design passes simulation but fails on the board, allowing you to probe internal signals, capture live silicon behavior, and verify fixes in real-time.

Quick Start

Invoke the ila-hw-debug skill to insert an ILA core and capture a waveform on the board for the current design.

Frequently Asked Questions about ila-hw-debug

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I debug an FPGA design that passes simulation but fails on physical hardware?▼

Debugging FPGA hardware failures requires inserting an Integrated Logic Analyzer (ILA) to probe internal signals and capture live silicon behavior, diagnosing real-time issues that simulation cannot replicate.

How do I capture waveforms from an FPGA using Vivado and JTAG?▼

Capturing FPGA waveforms via Vivado and JTAG involves orchestrating a hardware debug loop: programming the device, setting precise trigger conditions, and reading back real-time waveform data for analysis.

What is the best way to diagnose clock domain crossings on FPGA silicon?▼

Diagnosing clock domain crossings on FPGA silicon involves using an Integrated Logic Analyzer to monitor real-time signal behavior and I/O interactions directly on the physical hardware target.

Do I need a Vivado Tcl server connection to use an ILA for hardware debugging?▼

Yes, hardware-level FPGA debugging requires a functional Vivado Tcl server connection, a JTAG-connected hardware target, and a valid debug-enabled bitstream to execute the capture loop.

Can I automate the insertion and configuration of ILA debug cores into my FPGA design?▼

Yes, ILA orchestration automates the insertion, configuration, and connection of debug cores into your FPGA design, streamlining the setup process for capturing live signal behavior.

Why should I use hardware-level FPGA debugging instead of relying on simulation?▼

Hardware-level FPGA debugging is necessary because complex, non-deterministic behavior on physical FPGA hardware often cannot be replicated or observed in a simulation environment.

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