vivado-debug

Configure and troubleshoot Vivado debugging cores for FPGA designs.

2|Updated May 6, 2026

Search Tags:#debugging #vivado #vio #ila #jtag-to-axi #versal

Ready to run

npx skills add https://github.com/konosubakonoakua/xilinx-skills --skill vivado-debug-konosubakonoakua

💬 Prompt for ChatGPT / Claude Chat▼

Please help me install this Agent Skill.
Skill: vivado-debug
Source: https://github.com/konosubakonoakua/xilinx-skills/tree/main/vivado-debug
Command: npx skills add https://github.com/konosubakonoakua/xilinx-skills --skill vivado-debug-konosubakonoakua

SYSTEM DOCUMENTATION & REQUIREMENTS

What problem does it solve?

Vivado 调试与硬件编程中的决策和执行路径常常复杂且易出错。本 Skill 提供系统化的方法，帮助开发者在 ILA/VIO、AXI 调试、以及 Versal 调试架构中快速做出正确选择并配置调试核。

Core Features & Use Cases

ILA 配置与跨时钟触发的综合策略，包括数据深度、触发条件和探针分配。
VIO 的信号监控与控制，用于实时状态观察、复位控制和信号刺激。
JTAG-to-AXI Master 的事务创建、队列执行和 AXI4-Debug Hub 连接。
Versal AXI4 Debug Hub/ CIPS 集成的调试架构与替代 BSCAN 路径。
网表插入、TCL 自动化、SVF 编程及调试时序要求的完整工作流。
调试时序缓解策略与常见错误诊断指北，确保设计在实现阶段也可验证。

Quick Start

Use the guided workflow to configure an ILA and VIO for a target Vivado project and start hardware debugging.

Frequently Asked Questions about vivado-debug

High-intent search queries and answers about installing and using this skill.

FAQPage Schema

How do I configure ILA for cross-clock domain triggering in Vivado?▼

Configuring ILA for cross-clock domain triggering requires matching data depth, trigger conditions, and probe allocation. Apply implementation strategies and timing considerations to enable reliable signal tracing during Vivado hardware bring-up.

What is the best way to use VIO for signal monitoring and reset control?▼

The best way to use VIO for signal monitoring and reset control is to apply it for real-time status observation, reset control, and signal stimulation. This allows direct hardware manager operations to verify design behavior dynamically.

How do I create AXI transactions using JTAG-to-AXI Master?▼

Creating AXI transactions using JTAG-to-AXI Master involves transaction creation, queue execution, and connecting to the AXI4-Debug Hub. This workflow enables direct memory-mapped access and debugging for your FPGA design.

Does Vivado debugging support Versal AXI Debug Hub and CIPS integration?▼

Yes, Vivado debugging supports Versal AXI Debug Hub and CIPS integration by providing alternative BSCAN paths. This architecture allows you to configure debug cores specifically for Versal devices during hardware bring-up.

Why does Vivado debugging fail due to timing constraints during implementation?▼

Vivado debugging can fail due to timing constraints when implementation strategies do not meet debug timing requirements. Apply timing mitigation strategies and TCL scripting to diagnose errors and ensure the design remains verifiable.

Can I automate netlist insertion and SVF programming using TCL in Vivado?▼

You can automate netlist insertion and SVF programming using vivado-tcl scripts. This complete workflow handles implementation strategies and hardware manager operations to enable reliable debugging without manual intervention.