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vivado-debug

Guide selection, configuration, and deployment of Vivado debug cores for hardware debugging.

156|19|Updated Mar 27, 2026
Search Tags:#debugging#vivado#vio#tcl#ila#jtag-to-axi#versal
One-click install
npx skills add https://github.com/Shinei-Nouzen-Arch/FPGA-Agent-skills --skill vivado-debug
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: vivado-debug
Source: https://github.com/Shinei-Nouzen-Arch/FPGA-Agent-skills/tree/main/vivado-debug
Command: npx skills add https://github.com/Shinei-Nouzen-Arch/FPGA-Agent-skills --skill vivado-debug

SYSTEM DOCUMENTATION & REQUIREMENTS

What problem does it solve?

This skill helps FPGA developers and hardware engineers choose and implement effective debugging strategies for Vivado-based designs, covering ILA/VIO configuration, cross-trigger flows, AXI transactions, and hardware-manager workflows.

Core Features & Use Cases

  • Debug core selection and configuration (ILA, VIO, JTAG-to-AXI Master) based on timing, probes, and trigger needs.
  • Flow guidance for Netlist Insertion, HDL Instantiation, mark_debug, and Set Up Debug Wizard; cross-trigger coordination; Versal AXI4 Debug Hub integration.
  • Practical troubleshooting, timing impact mitigation, SVF/BD programming workflows, and hardware programming steps.

Quick Start

Learn to select and configure ILA/VIO/JTAG-to-AXI Master flows for Vivado hardware debugging, then use TCL commands to implement and program the device.

Frequently Asked Questions about vivado-debug

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I configure ILA and VIO debug cores in Vivado for hardware debugging?▼

Vivado debug core configuration involves selecting ILA or VIO based on trigger and probe requirements, then using netlist insertion, HDL instantiation, or the Set Up Debug Wizard to deploy them. TCL automation commands streamline implementation and device programming.

What is the best way to use JTAG-to-AXI Master for debugging in Vivado?▼

The JTAG-to-AXI Master facilitates AXI transaction debugging in Vivado by driving AXI traffic through JTAG. Configuring it allows direct memory-mapped register access and peripheral testing without requiring full logic redesign.

Does Vivado debug flow support Versal designs and AXI4 Debug Hub integration?▼

Yes, Vivado debug flows support Versal designs through AXI4 Debug Hub integration. This architecture enables coordinated debug core management and cross-trigger setups specifically tailored for Versal hardware structures.

How do I automate Vivado debug core deployment using TCL commands?▼

Automate Vivado debug deployment by applying TCL commands to instantiate ILA and VIO cores, set mark_debug attributes on nets, and program the target device. This streamlines repetitive hardware debugging workflows.

Why does adding ILA debug cores cause timing violations in Vivado?▼

Adding ILA debug cores introduces routing congestion and logic delays that can cause timing violations. Mitigating timing impact requires careful probe selection, sample depth optimization, and strategic clock domain placement.

Can I use cross-trigger architectures to coordinate multiple ILA cores in Vivado?▼

Cross-trigger architectures in Vivado coordinate multiple ILA cores by linking trigger inputs and outputs across different clock domains. This setup enables synchronized capture of complex, multi-domain hardware events.

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