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vivado-debug

Community

Decide and deploy Vivado debug flows efficiently.

Software Engineering#debugging#vivado#vio#tcl#ila#jtag-to-axi#versal
AuthorShinei-Nouzen-Arch
Version1.0.0
Installs0

System Documentation

What problem does it solve?

This skill helps FPGA developers and hardware engineers choose and implement effective debugging strategies for Vivado-based designs, covering ILA/VIO configuration, cross-trigger flows, AXI transactions, and hardware-manager workflows.

Core Features & Use Cases

  • Debug core selection and configuration (ILA, VIO, JTAG-to-AXI Master) based on timing, probes, and trigger needs.
  • Flow guidance for Netlist Insertion, HDL Instantiation, mark_debug, and Set Up Debug Wizard; cross-trigger coordination; Versal AXI4 Debug Hub integration.
  • Practical troubleshooting, timing impact mitigation, SVF/BD programming workflows, and hardware programming steps.

Quick Start

Learn to select and configure ILA/VIO/JTAG-to-AXI Master flows for Vivado hardware debugging, then use TCL commands to implement and program the device.

Dependency Matrix

Required Modules

None required

Components

Standard package

💻 Claude Code Installation

Recommended: Let Claude install automatically. Simply copy and paste the text below to Claude Code.

Please help me install this Skill:
Name: vivado-debug
Download link: https://github.com/Shinei-Nouzen-Arch/FPGA-Agent-skills/archive/main.zip#vivado-debug

Please download this .zip file, extract it, and install it in the .claude/skills/ directory.
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