shinei-nouzen-arch
Community@shinei-nouzen-arch
Former employees of Hisilicon. Mphil in Computer and Information Engineering. I am currently seeking a doctoral position in the field of computer architecture.
Agent Skills by shinei-nouzen-arch
Showing 8 vetted skills indexed across 1 GitHub repositories.
vitis-hls-synthesis
Converts C/C++ FPGA kernels to RTL using Vitis HLS.
vivado-sim
Plan and execute Vivado simulations for behavioral, post-synthesis, and timing verification.
vivado-tcl
Generate and execute Vivado/Vitis TCL scripts for FPGA design flows.
vivado-impl
Guide FPGA Vivado implementation decisions for timing closure and resource optimization.
vivado-constraints
Guide Vivado XDC/SDC timing and physical constraint creation for FPGA designs.
vivado-debug
Guide selection, configuration, and deployment of Vivado debug cores for hardware debugging.
vivado-analysis
Interpret Vivado timing and QoR reports to guide timing closure decisions.
vivado-synth
Identify optimal Vivado synthesis strategies and attribute configurations for QoR.