vitis-hls-synthesis

Vitis HLS synthesis assistant for C/C++ to RTL conversion. Covers kernel development, pragma optimization, interface configuration, and synthesis report analysis. For post-synthesis implementation use vivado-impl, for timing analysis use vivado-analysis, for hardware debug use vivado-debug.

What problem does it solve?

Streamlines converting high-level C/C++ FPGA kernels into RTL and orchestrates the complete synthesis flow, reducing development time and enabling rapid iteration across device families.

Core Features & Use Cases

• Kernel development: write C/C++ kernels and map them to hardware using Vitis HLS.
• Pragma optimization: apply and tune PIPELINE, UNROLL, DATAFLOW, ARRAY_PARTITION, and related pragmas for performance/area trade-offs.
• Interface configuration: configure memory and peripheral interfaces (m_axi, axis, s_axilite, etc.) and manage data movement bottlenecks.
• Flow orchestration: run C simulation, C synthesis, co-simulation, and packaging into IP or Vitis kernels, with access to synthesis reports (timing, resources, II).
• Cross-device targeting: re-target IP across AMD FPGA/adaptive SoC families with config-driven migration steps.

Quick Start

Create a Vitis HLS component, implement your kernel, set the top function and clock, then run the Vitis HLS flow (csim → csynth → cosim → package) and review the generated reports.