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vitis-hls-synthesis

Converts C/C++ FPGA kernels to RTL using Vitis HLS.

156|19|Updated Mar 27, 2026
Search Tags:#flow#rtl#hls#fpga#pragmas#vitis-hls
One-click install
npx skills add https://github.com/Shinei-Nouzen-Arch/FPGA-Agent-skills --skill vitis-hls-synthesis
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: vitis-hls-synthesis
Source: https://github.com/Shinei-Nouzen-Arch/FPGA-Agent-skills/tree/main/vitis-hls-synthesis
Command: npx skills add https://github.com/Shinei-Nouzen-Arch/FPGA-Agent-skills --skill vitis-hls-synthesis

SYSTEM DOCUMENTATION & REQUIREMENTS

Vitis HLS synthesis assistant for C/C++ to RTL conversion. Covers kernel development, pragma optimization, interface configuration, and synthesis report analysis. For post-synthesis implementation use vivado-impl, for timing analysis use vivado-analysis, for hardware debug use vivado-debug.

What problem does it solve?

Streamlines converting high-level C/C++ FPGA kernels into RTL and orchestrates the complete synthesis flow, reducing development time and enabling rapid iteration across device families.

Core Features & Use Cases

  • Kernel development: write C/C++ kernels and map them to hardware using Vitis HLS.
  • Pragma optimization: apply and tune PIPELINE, UNROLL, DATAFLOW, ARRAY_PARTITION, and related pragmas for performance/area trade-offs.
  • Interface configuration: configure memory and peripheral interfaces (m_axi, axis, s_axilite, etc.) and manage data movement bottlenecks.
  • Flow orchestration: run C simulation, C synthesis, co-simulation, and packaging into IP or Vitis kernels, with access to synthesis reports (timing, resources, II).
  • Cross-device targeting: re-target IP across AMD FPGA/adaptive SoC families with config-driven migration steps.

Quick Start

Create a Vitis HLS component, implement your kernel, set the top function and clock, then run the Vitis HLS flow (csim → csynth → cosim → package) and review the generated reports.

Frequently Asked Questions about vitis-hls-synthesis

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I convert C or C++ code to RTL for an FPGA using Vitis HLS?▼

Vitis HLS translates C/C++ FPGA kernels into RTL by running a synthesis flow that includes C simulation, synthesis, co-simulation, and packaging into IP or Vitis kernels. You configure the top function, clock, and target AMD device to generate the RTL output.

How do I optimize HLS pragmas like PIPELINE and DATAFLOW for better FPGA performance?▼

You apply and tune HLS pragmas such as PIPELINE, UNROLL, DATAFLOW, and ARRAY_PARTITION to balance performance and area trade-offs. These directives control loop execution, parallelism, and memory bandwidth to achieve lower initiation intervals and reduced resource usage.

Can I configure AXI interfaces for memory and peripherals in C/C++ HLS kernels?▼

Yes, Vitis HLS supports interface configuration for m_axi, axis, and s_axilite protocols. You map function arguments to these AXI interfaces to manage data movement and connect your synthesized RTL to memory and peripheral blocks on the FPGA.

What is the best way to target multiple AMD FPGA devices with the same C/C++ kernel?▼

You can re-target IP across AMD FPGA and adaptive SoC families using config-driven migration steps. By updating the Vitis HLS configuration files, you change the target device and re-run the synthesis flow without rewriting the original C/C++ kernel.

How do I analyze timing and resource utilization after Vitis HLS synthesis?▼

After running C synthesis, Vitis HLS generates detailed synthesis reports covering timing, resource utilization, and initiation intervals. You review these reports to evaluate whether the generated RTL meets your performance and area constraints.

Why does my Vitis HLS flow stop after C synthesis, and do I need another tool for implementation?▼

Vitis HLS focuses on C/C++ to RTL synthesis and packaging. For post-synthesis implementation, timing analysis, and hardware debug, you need to use vivado-impl, vivado-analysis, and vivado-debug respectively to complete the hardware deployment flow.

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