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vitis-hls-synthesis

Guide C/C++ to RTL translation with Vitis HLS pragma optimization and synthesis reports.

2|Updated May 6, 2026
Search Tags:#c++#rtl#hls#fpga#vivado
One-click install
npx skills add https://github.com/konosubakonoakua/xilinx-skills --skill vitis-hls-synthesis-konosubakonoakua
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: vitis-hls-synthesis
Source: https://github.com/konosubakonoakua/xilinx-skills/tree/main/vitis-hls-synthesis
Command: npx skills add https://github.com/konosubakonoakua/xilinx-skills --skill vitis-hls-synthesis-konosubakonoakua

SYSTEM DOCUMENTATION & REQUIREMENTS

What problem does it solve?

The Vitis HLS synthesis assistant helps hardware engineers streamline kernel development, pragma-driven optimization, interface configuration, and RTL generation by providing a structured workflow and best practices.

Core Features & Use Cases

  • Guided C/C++ to RTL translation for HLS-based FPGA design, including end-to-end workflows from CSIM to CO_SIM and implementation.
  • Comprehensive pragma support (PIPELINE, UNROLL, DATAFLOW, ARRAY_PARTITION) and interface optimization to balance performance and resource usage.
  • Integrated flow configuration and reporting guidance, enabling quick interpretation of Vivado synthesis and timing reports and easy retargeting across devices.
  • Reusable patterns and templates for common FPGA workloads, rapid migration between Vitis HLS and Vivado flows, and hands-on examples for ARM/desktop environments.

Quick Start

Start with the provided HLS skeleton and guided steps to generate RTL for a sample kernel.

Frequently Asked Questions about vitis-hls-synthesis

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I optimize C++ to RTL translation using Vitis HLS pragmas?▼

Vitis HLS translation optimizes C++ to RTL by guiding pragma insertion for PIPELINE, UNROLL, DATAFLOW, and ARRAY_PARTITION to balance performance and resource usage during kernel development.

What's the best way to set up a Vitis HLS project from CSIM to implementation?▼

The Vitis HLS workflow guides end-to-end setup from CSIM to CO_SIM and implementation, providing structured steps for project configuration, kernel development, and RTL generation.

Can I retarget FPGA synthesis across different devices using Vivado and Vitis?▼

Device retargeting across Vivado and Vitis toolchains is supported through integrated flow configuration, enabling quick migration between Vitis HLS and Vivado flows for different target devices.

How do I interpret Vivado synthesis and timing reports after HLS generation?▼

RTL generation includes integrated reporting guidance to help interpret Vivado synthesis and timing reports, enabling quick analysis of resource usage and timing metrics for optimized kernels.

Does Vitis HLS support interface configuration for ARM and desktop environments?▼

Vitis HLS provides reusable patterns and templates for common FPGA workloads, including hands-on examples for interface configuration across ARM and desktop environments.

Why use HLS for FPGA design instead of writing RTL directly?▼

HLS for FPGA design streamlines kernel development through structured workflows and best practices, accelerating RTL generation from C++ while applying pragma-driven optimization to balance performance and resources.

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