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vivado-synth

Identify optimal Vivado synthesis strategies and attribute configurations for QoR.

156|19|Updated Mar 27, 2026
Search Tags:#synthesis#rtl#fpga#hdl#vivado#tcl
One-click install
npx skills add https://github.com/Shinei-Nouzen-Arch/FPGA-Agent-skills --skill vivado-synth-shinei-nouzen-arch
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: vivado-synth
Source: https://github.com/Shinei-Nouzen-Arch/FPGA-Agent-skills/tree/main/vivado-synth
Command: npx skills add https://github.com/Shinei-Nouzen-Arch/FPGA-Agent-skills --skill vivado-synth-shinei-nouzen-arch

SYSTEM DOCUMENTATION & REQUIREMENTS

What problem does it solve?

This skill helps engineers choose appropriate Vivado synthesis strategies, options, and attributes to optimize area, timing, and power while meeting project constraints.

Core Features & Use Cases

  • Choose synthesis strategies and directives to optimize QoR across RTL-to-synthesis flows.
  • Configure resource mapping and hierarchy controls (RAM_STYLE/USE_DSP/SHREG_EXTRACT, flatten_hierarchy, KEEP_HIERARCHY) and pattern-based synthesis for OOC or incremental flows.
  • Support RTL linting and Block-Level synthesis (BLOCK_SYNTH) planning to balance QoR across modules and IP blocks.

Quick Start

Tell me your QoR priorities and target part, and I will propose a synthesis strategy and attribute plan.

Frequently Asked Questions about vivado-synth

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I choose the right Vivado synthesis directives to optimize timing and area?▼

Vivado synthesis directives are chosen by evaluating your QoR priorities and target part to balance area, timing, and power trade-offs. This approach matches directive selection and resource inference controls like USE_DSP to your specific design constraints.

What is the best way to configure RAM_STYLE and USE_DSP attributes for FPGA synthesis?▼

Configuring RAM_STYLE and USE_DSP attributes requires mapping resources based on your desired QoR. This involves selecting appropriate synthesis strategies to control pattern-based resource inference, ensuring optimal logic distribution across the FPGA fabric.

When do I need out-of-context or incremental synthesis flows in Vivado?▼

Out-of-context and incremental synthesis flows are needed when managing complex designs where block-level QoR balancing is critical. These flows use hierarchy controls like flatten_hierarchy and KEEP_HIERARCHY to isolate modules and reduce runtime.

Can I balance QoR across specific modules using block-level synthesis?▼

Yes, block-level synthesis balances QoR across specific modules and IP blocks. By applying BLOCK_SYNTH planning and localized attribute configurations, you can independently optimize individual modules without affecting the entire design.

Why does flatten_hierarchy affect my Vivado synthesis results and timing closure?▼

Flatten_hierarchy affects synthesis results by removing logical boundaries to allow cross-boundary optimization. Adjusting this hierarchy option changes how the tool processes logic, heavily influencing timing closure and resource inference outcomes.

How do I control FSM extraction and SHREG_EXTRACT during RTL synthesis?▼

FSM extraction and SHREG_EXTRACT are controlled by applying specific synthesis attributes to your RTL. This guides the tool's pattern recognition for state machines and shift registers, directly impacting overall area and timing QoR.

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