Automate Xilinx Vivado FPGA simulation, synthesis, and bitstream generation.
npx skills add https://github.com/hnabyz-bot/gate_drv --skill moai-vivado
Please help me install this Agent Skill. Skill: moai-vivado Source: https://github.com/hnabyz-bot/gate_drv/tree/main/.claude/skills/moai-vivado Command: npx skills add https://github.com/hnabyz-bot/gate_drv --skill moai-vivado
This skill provides a structured approach to automate and orchestrate Xilinx Vivado FPGA development tasks, covering RTL simulation with XSim, synthesis, implementation, and bitstream generation.
Install Vivado 2024.2 or newer, then run the provided TCL scripts to perform simulation and synthesis tasks without GUI.
High-intent search queries and answers about installing and using this skill.
Automating Vivado batch mode uses Tcl scripts to execute synthesis, place-and-route, and bitstream generation without the GUI. This skill orchestrates that end-to-end flow for Artix-7 devices, generating project reports and bitstreams.
Running XSim RTL simulation in CI workflows coordinates xvlog, xelab, and xsim command-line tools. This skill structures those simulation commands to validate SystemVerilog designs with proper timescale directives.
This FPGA workflow targets Artix-7 devices specifically for synthesis and bitstream generation. It applies Vivado batch-based implementation flows to produce bitstreams for this Xilinx hardware family.
Vivado 2024.2 or newer is required to run the provided Tcl scripts for simulation and synthesis tasks. Installing this version ensures compatibility with the batch-based end-to-end FPGA flow.
Timescale directives are required during XSim simulation to define the time precision and unit for SystemVerilog models. This skill satisfies those requirements to ensure accurate model validation and simulation timing.
pjy4617Automate Verilog/SystemVerilog simulation workflows using Vivado xsim.
pjy4617Generate Vivado bitstreams from post-route checkpoints and program FPGAs via TCL scripts.
x-meshAutomate build script execution for software development workflows.
chuanseng-ngAutomate ASIC RTL adaptation, synthesis, and bring-up for FPGA prototypes.
