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vivado-project

Automate Vivado project setup, board selection, and RTL source management with XDC constraints.

Updated Mar 17, 2026
Search Tags:#automation#constraints#project-management#fpga#vivado#xdc#board-switching
One-click install
npx skills add https://github.com/pjy4617/pjy-claude-skill --skill vivado-project
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: vivado-project
Source: https://github.com/pjy4617/pjy-claude-skill/tree/main/plugins/vivado/skills/vivado-project
Command: npx skills add https://github.com/pjy4617/pjy-claude-skill --skill vivado-project

SYSTEM DOCUMENTATION & REQUIREMENTS

What problem does it solve?

FPGA 프로젝트를 초기화하고 보드를 바꿀 때마다 반복되는 설정과 제약 조건 적용 작업을 자동화하여 실수를 줄이고 생산성을 높입니다. 이 스킬은 보드별 설정을 표준화하고 소스 관리, RTL/제약 파일의 일관된 구성을 돕습니다.

Core Features & Use Cases

  • Board-aware 프로젝트 생성 및 파트/클럭/제약 설정 자동화
  • Master XDC를 통한 제약 관리 및 보드 간 원활한 교체
  • RTL 모듈 추가 및 소스 구성 유지 보수의 자동화

Quick Start

Create a new Vivado project, switch the target board, and add modules with the correct constraints.

Frequently Asked Questions about vivado-project

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I automate Vivado project setup and board switching for FPGA development?▼

Automating Vivado project setup uses CLI batch mode to read boards.json for part, clock, and constraint mappings, enabling seamless target board switching and source management without manual reconfiguration errors.

What is the best way to manage XDC constraints when switching FPGA boards in Vivado?▼

Managing XDC constraints during board switching relies on master XDC references, which standardize constraint application across different target boards defined in the boards.json configuration file.

Can I use CLI batch mode to add RTL modules and configure clocks in Vivado?▼

Yes, CLI batch mode automates adding RTL modules and configuring clocks by reading specific part and clock parameters from the boards.json file, ensuring consistent source integration.

Do I need a boards.json file to automate Vivado project creation?▼

Yes, a boards.json file is required to automate Vivado project creation, as it provides the necessary part numbers, clock settings, and constraint mappings for the target FPGA board.

Why does my Vivado board switching workflow keep breaking XDC constraints?▼

Vivado board switching breaks XDC constraints when configurations are applied manually, which this automation Skill prevents by standardizing settings and applying constraints directly from master XDC sources.

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