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fpga

Provide version-aware FPGA design guidance for Vivado-based RTL projects.

2|Updated Jan 30, 2026
Search Tags:#verification#rtl#fpga#systemverilog#vivado#verilog#tcl
One-click install
npx skills add https://github.com/george11642/george-plugins --skill fpga
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: fpga
Source: https://github.com/george11642/george-plugins/tree/main/plugins/fpga-dev/skills/fpga
Command: npx skills add https://github.com/george11642/george-plugins --skill fpga

SYSTEM DOCUMENTATION & REQUIREMENTS

What problem does it solve?

This skill provides version-aware FPGA design guidance and Context7-backed documentation to streamline Vivado-based RTL projects and reduce integration risk.

Core Features & Use Cases

  • Version-aware Vivado workflows tailored to specific releases (2017–2023).
  • Context7 MCP integration to fetch up-to-date FPGA docs, AXI/IP references, and verification patterns.
  • Comprehensive guidance on synchronous design, CDC handling, timing constraints, and IP usage for RTL development.

Quick Start

Identify your target Vivado version and device, then generate a version-tuned TCL plan and RTL design checklist.

Frequently Asked Questions about fpga

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I handle clock domain crossing in Vivado-based RTL projects?▼

Clock domain crossing (CDC) handling in Vivado-based RTL projects requires proper CDC constraints and synchronization logic to prevent metastability. This skill provides version-aware guidance on CDC handling, ensuring safe data transfer between asynchronous clock domains across Vivado releases 2017–2023.

What is the best way to achieve timing closure for FPGA designs in Vivado?▼

Timing closure for FPGA designs in Vivado involves applying precise timing constraints and optimizing RTL logic to meet setup and hold requirements. This skill offers version-tuned TCL commands and timing constraint guidance to streamline timing closure across multiple Vivado releases.

Does this FPGA design guidance support specific Vivado versions like 2017 or 2023?▼

This FPGA design guidance supports Vivado versions spanning from 2017 through 2023 and beyond. It ensures compatibility by applying version-tuned TCL commands, IP usage rules, and constraint methodologies specific to your target Vivado release.

How do I generate a TCL plan for AXI interfacing in SystemVerilog?▼

Generating a TCL plan for AXI interfacing in SystemVerilog involves fetching up-to-date AXI/IP references and applying version-specific TCL commands. This skill uses Context7 MCP integration to retrieve current documentation and enforce proper AXI interface patterns.

Why does my RTL verification fail across different Vivado releases?▼

RTL verification failures across different Vivado releases often stem from incompatible IP usage, outdated TCL commands, or improper CDC constraints. This skill provides version-aware verification support and up-to-date documentation to ensure consistent hardware verification across Vivado 2017–2023+.

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