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fpga

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Master FPGA design with Vivado and RTL

Software Engineering#verification#rtl#fpga#systemverilog#vivado#verilog#tcl
Authorgeorge11642
Version1.0.0
Installs0

System Documentation

What problem does it solve?

This skill provides version-aware FPGA design guidance and Context7-backed documentation to streamline Vivado-based RTL projects and reduce integration risk.

Core Features & Use Cases

  • Version-aware Vivado workflows tailored to specific releases (2017–2023).
  • Context7 MCP integration to fetch up-to-date FPGA docs, AXI/IP references, and verification patterns.
  • Comprehensive guidance on synchronous design, CDC handling, timing constraints, and IP usage for RTL development.

Quick Start

Identify your target Vivado version and device, then generate a version-tuned TCL plan and RTL design checklist.

Dependency Matrix

Required Modules

None required

Components

Standard package

💻 Claude Code Installation

Recommended: Let Claude install automatically. Simply copy and paste the text below to Claude Code.

Please help me install this Skill:
Name: fpga
Download link: https://github.com/george11642/george-plugins/archive/main.zip#fpga

Please download this .zip file, extract it, and install it in the .claude/skills/ directory.
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