飞
Community@konosubakonoakua · NGC 2068
🌪面向巧合编程🌪
Agent Skills by 飞
Showing 13 vetted skills indexed across 1 GitHub repositories.
vivado-git
Organize Vivado projects under Git for reproducible hardware development.
vitis-hls-synthesis
Guide C/C++ to RTL translation with Vitis HLS pragma optimization and synthesis reports.
vivado-sim
Guide Vivado simulation workflows for RTL, post-synthesis, and post-implementation verification.
pynq
Create and customize PYNQ-based FPGA images and overlays for custom boards.
vivado-tcl
Generate and execute Vivado/Vitis TCL scripts for FPGA design automation.
axion-hdl
Generate AXI4-Lite register interfaces from YAML/JSON or HDL annotations.
petalinux
Configure and build PetaLinux projects for Xilinx Zynq/MPSoC/Versal platforms.
vivado-impl
Guide Vivado implementation flows from synthesis to routing with optimization commands.
vivado-constraints
Define and manage FPGA timing and placement constraints with Vivado XDC/SDC.
vivado-debug
Configure and troubleshoot Vivado debugging cores for FPGA designs.
vivado-analysis
Explain Vivado timing and design analysis reports for convergence decisions.
vivado-synth
Guide Vivado synthesis strategy and resource-mapping control selection.
xilinx-docs
Locate AMD Xilinx documentation by document ID and return official links.