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vivado-synth

Guide Vivado synthesis strategy and resource-mapping control selection.

2|Updated May 6, 2026
Search Tags:#synthesis#rtl#fpga#vivado#ooc#block_synth#retiming
One-click install
npx skills add https://github.com/konosubakonoakua/xilinx-skills --skill vivado-synth-konosubakonoakua
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: vivado-synth
Source: https://github.com/konosubakonoakua/xilinx-skills/tree/main/vivado-synth
Command: npx skills add https://github.com/konosubakonoakua/xilinx-skills --skill vivado-synth-konosubakonoakua

SYSTEM DOCUMENTATION & REQUIREMENTS

What problem does it solve?

This skill provides decision-grade guidance for selecting Vivado synthesis strategies, options, and resource-mapping controls. It helps engineers balance area, timing, and power while managing hierarchical flattening, OOC synthesis, incremental runs, RTL linting, and BLOCK_SYNTH configurations. It does not execute commands itself but informs TAC decisions and best practices, and points to the appropriate Vivado TCL commands when needed.

Core Features & Use Cases

  • Guidance on choosing synthesis strategies, directives, and attributes (flatten_hierarchy, KEEP_HIERARCHY, RAM/BRAM/ DSP usage) based on project goals.
  • Supports planning for out-of-context synthesis, incremental builds, RTL linting, and per-instance BLOCK_SYNTH settings to optimize QoR.
  • Use Case: A design approaching a timing bottleneck can be steered toward PerformanceOptimized, or a resource-constrained design toward AreaOptimized strategies, while preserving hierarchy and reproducibility.

Quick Start

Propose a Vivado synthesis strategy and settings for my project to achieve the best balance of area and timing while keeping the RTL structure intact.

Frequently Asked Questions about vivado-synth

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I choose the right Vivado synthesis strategy for balancing FPGA area and timing?▼

Selecting Vivado synthesis strategies involves choosing PerformanceOptimized for timing bottlenecks or AreaOptimized for resource limits, using directives and attributes to balance FPGA area and timing.

What does flatten_hierarchy do during RTL synthesis in Vivado?▼

The flatten_hierarchy option in Vivado controls hierarchical flattening during RTL synthesis, allowing you to preserve the RTL structure or flatten it to optimize logic optimization and timing across module boundaries.

When should I use out-of-context synthesis for my FPGA design?▼

Use out-of-context (OOC) synthesis to synthesize modules independently, enabling incremental builds and preserving synthesis results for reusable blocks to improve compile time reproducibility.

How do I configure BLOCK_SYNTH settings for RAM and DSP resource mapping?▼

Configure BLOCK_SYNTH settings by applying per-instance attributes to customize RAM, BRAM, and DSP resource mapping, allowing granular control over how specific logic blocks are inferred and optimized during synthesis.

Does this skill provide the actual TCL commands for running Vivado synthesis?▼

No, this skill does not execute commands, but it informs synthesis planning decisions and points you to the appropriate Vivado TCL commands and UG901-based guidelines needed for your implementation.

What is the best way to preserve hierarchy while optimizing timing in Vivado synthesis?▼

The best way to preserve hierarchy while optimizing timing is to use KEEP_HIERARCHY attributes alongside PerformanceOptimized strategies, ensuring safe and reproducible synthesis planning without sacrificing cross-boundary optimizations.

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