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constraints-authoring

Author and verify Vivado XSD timing constraints for FPGA designs.

11|7|Updated Jun 5, 2026
Search Tags:#synthesis#constraints#timing#fpga#vivado#xdc
One-click install
npx skills add https://github.com/LNC0831/oh-my-fpga --skill constraints-authoring
Or copy as Structured Prompt for Agent▼
Please help me install this Agent Skill.
Skill: constraints-authoring
Source: https://github.com/LNC0831/oh-my-fpga/tree/main/skills/constraints-authoring
Command: npx skills add https://github.com/LNC0831/oh-my-fpga --skill constraints-authoring

SYSTEM DOCUMENTATION & REQUIREMENTS

What problem does it solve?

This skill solves the common FPGA engineering challenge of creating a correct, honest, and complete set of timing constraints (XDC) from scratch, ensuring the timing engine understands the design's true requirements rather than relying on incomplete or optimistic defaults.

Core Features & Use Cases

  • Systematic Constraint Authoring: Guides the user through defining primary clocks, generated clocks, I/O delays, and timing exceptions in the correct dependency order.
  • Verification-First Workflow: Mandates post-synthesis verification using check_timing and clock network reports to ensure constraints are physically grounded in the netlist.
  • Use Case: Use this when starting a new FPGA project with no constraints, or when your current design reports unconstrained clocks, missing I/O delays, or failing paths due to incorrectly modeled asynchronous clock domains.

Quick Start

Invoke the constraints-authoring skill to begin defining your primary clocks and I/O delays for a new design that currently has no timing constraints.

Frequently Asked Questions about constraints-authoring

High-intent search queries and answers about installing and using this skill.

FAQPage Schema
How do I write Vivado XDC constraints for a new FPGA design from scratch?▼

Authoring Vivado XDC constraints from scratch requires defining primary clocks, generated clocks, I/O budgets, and timing exceptions in dependency order based on board-level specifications and design intent to ensure the timing engine understands true requirements.

What is the best way to resolve unconstrained clocks and missing I/O delays in XDC?▼

Resolving unconstrained clocks and missing I/O delays involves authoring a complete XDC constraint set and performing post-synthesis verification using check_timing and clock network reports to validate clock network relationships against the synthesized netlist.

How do I verify FPGA timing exceptions against a synthesized netlist?▼

Verifying FPGA timing exceptions against a synthesized netlist involves running post-synthesis check_timing and clock network reports to confirm zero unintended unconstrained objects and validate clock network relationships.

When do I need to define generated clocks and I/O budgets in XDC?▼

Defining generated clocks and I/O budgets in XDC is necessary when starting a new FPGA project with no constraints or when a design reports failing paths due to incorrectly modeled asynchronous clock domains.

Why does my FPGA design report failing paths due to incorrectly modeled asynchronous clock domains?▼

FPGA designs report failing paths due to incorrectly modeled asynchronous clock domains when relying on incomplete or optimistic defaults instead of a complete, verified XDC constraint set defining true timing requirements and necessary timing exceptions.

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