Agent Skills by Xiaochuan5305
Showing 13 vetted skills indexed across 1 GitHub repositories.
LNC0831zynq-bringup
Orchestrates instantiation, configuration, and verification of Zynq-7000 Processing System block designs.
LNC0831full-flow-demo
Orchestrate the Xilinx FPGA build flow from RTL simulation to bitstream generation.
LNC0831timing-closure
Orchestrate iterative timing closure for FPGA designs in Vivado.
LNC0831constraints-authoring
Author and verify Vivado XSD timing constraints for FPGA designs.
LNC0831ila-hw-debug
Insert Integrated Logic Analyzers and execute hardware debug cycles on FPGA silicon.
LNC0831power-optimization
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LNC0831utilization-reduction
Diagnose and mitigate FPGA resource overutilization in SynthPilot MCP.
LNC0831sim-bringup
Orchestrate behavioral RTL simulation pipelines with xvlog, xvhdl, and xelab.
LNC0831coverage-closure
Orchestrate RTL simulation coverage closure for FPGA designs.
LNC0831bitstream-program
Generate FPGA bitstreams and program JTAG or SPI/BPI flash memory devices.
LNC0831qor-report
Generate an FPGA design-health scorecard from Vivado timing, utilization, power, and congestion metrics.
LNC0831cdc-audit
Audit and resolve clock-domain-crossing risks in FPGA netlists.
LNC0831lint-triage
Automates RTL linting and methodology violation triage via SynthOol tools.