Orchestrate the Xilinx FPGA build flow from RTL simulation to bitstream generation.
npx skills add https://github.com/LNC0831/oh-my-fpga --skill full-flow-demo
Please help me install this Agent Skill. Skill: full-flow-demo Source: https://github.com/LNC0831/oh-my-fpga/tree/main/skills/full-flow-demo Command: npx skills add https://github.com/LNC0831/oh-my-fpga --skill full-flow-demo
This skill solves the problem of fragmented FPGA development by providing a structured, gated orchestration layer that ensures every stage of the build process—from RTL to bitstream—is verified before proceeding.
Invoke the full-flow-demo skill to run the complete build sequence from RTL to bitstream for the current project.
High-intent search queries and answers about installing and using this skill.
To automate the complete FPGA build flow, you can use an orchestration skill that sequences RTL simulation, synthesis, implementation, and bitstream generation. This enforces stage-by-stage verification gates to prevent silent regressions before generating the final bitstream.
Stage-by-stage gating is a verification mechanism that enforces strict checks across syntax, simulation, CDC, synthesis, and implementation phases. It ensures every stage of the FPGA build process is proven by tool reports before proceeding to the next step.
To ensure timing closure and DRC compliance, you need automated signoff validation on the implemented design. This process checks setup and hold timing, routing, and methodology reports, blocking bitstream generation until all metrics pass.
Yes, you need an active SynthPilot MCP connection to a Vivado Tcl server. This connection is required to execute tool commands, sequence the build flow, and validate design metrics during synthesis and implementation.
The best way to prevent silent regressions is to use a gated orchestration layer for your FPGA build. By validating design metrics and enforcing rigorous stage-by-stage verification, the flow halts if timing closure or DRC compliance fails.
Yes, full-flow-demo is designed to take complex designs from source files to a production-ready bitstream. It ensures every build step is verified through automated signoff, validating timing, routing, and DRC compliance before completion.
LNC0831Orchestrate behavioral RTL simulation pipelines with xvlog, xvhdl, and xelab.
LNC0831Insert Integrated Logic Analyzers and execute hardware debug cycles on FPGA silicon.
babywormGenerate CDC verification policies, SDC constraint patterns, and synchronizer guidance for RTL designs.
pjy4617Automate Vivado synthesis, implementation, and bitstream generation workflows.
