Orchestrate behavioral RTL simulation pipelines with xvlog, xvhdl, and xelab.
npx skills add https://github.com/LNC0831/oh-my-fpga --skill sim-bringup
Please help me install this Agent Skill. Skill: sim-bringup Source: https://github.com/LNC0831/oh-my-fpga/tree/main/skills/sim-bringup Command: npx skills add https://github.com/LNC0831/oh-my-fpga --skill sim-bringup
This skill solves the challenge of bringing up behavioral RTL simulations by providing a structured, repeatable methodology for compiling, elaborating, and diagnosing simulation failures without manual tool-chain guesswork.
Invoke the sim-bringup skill to compile and run the simulation for the top-level testbench module named tb_processor.
High-intent search queries and answers about installing and using this skill.
RTL simulation can be orchestrated by invoking the xsim engine to compile and execute your testbench. This skill automates the xvlog, xvhdl, and xelab pipeline stages to bypass manual GUI interactions.
Simulation elaboration failures are classified through a systematic diagnostic table mapping errors to safe fixes. This isolates root causes like unresolved modules or X-propagation without manual tool-chain guesswork.
Running xsim requires an active Vivado Tcl server connection and a properly configured project simulation fileset. These prerequisites ensure the behavioral simulation pipeline can access the necessary RTL sources.
Debugging X-propagation and runtime failures is supported by applying a structured diagnostic methodology. It maps simulation failures to specific fixes, allowing you to methodically isolate the root cause.
Testbench authoring and diagnostic analysis are automated by orchestrating the simulation pipeline within the SynthPilot environment. This provides a repeatable workflow for functional debugging and failure classification.
Both VHDL and Verilog compilation are supported through the xsim engine's xvlog and xvhdl stages. The pipeline orchestrates these tools to elaborate and execute the design for functional verification.
LNC0831Orchestrate the Xilinx FPGA build flow from RTL simulation to bitstream generation.
MameMame777Guide engineers from verification failures to RTL root causes.
chuanseng-ngAutomate ASIC RTL adaptation, synthesis, and bring-up for FPGA prototypes.
pjy4617Automate Verilog/SystemVerilog simulation workflows using Vivado xsim.
