Orchestrate RTL simulation coverage closure for FPGA designs.
npx skills add https://github.com/LNC0831/oh-my-fpga --skill coverage-closure
Please help me install this Agent Skill. Skill: coverage-closure Source: https://github.com/LNC0831/oh-my-fpga/tree/main/skills/coverage-closure Command: npx skills add https://github.com/LNC0831/oh-my-fpga --skill coverage-closure
This Skill solves the challenge of achieving sign-off grade code coverage in FPGA designs by providing a structured, methodology-driven approach to identifying and closing coverage gaps through targeted testbench stimulus.
Invoke the coverage-closure skill to analyze the current simulation results and identify untested branches in the design.
High-intent search queries and answers about installing and using this skill.
To close RTL simulation coverage gaps, this Skill parses simulation results to pinpoint untested files and branches, then guides you to add targeted stimulus or document exclusions to reach sign-off grade coverage.
The best way to improve branch and condition coverage is using a methodology-driven approach that classifies untested code, determining whether to add testbench stimulus, document an exclusion, or flag unreachable RTL code.
Yes, you need a valid Pro license and the SynthPilot MCP server with Vivado installed to execute RTL simulation coverage analysis and generate coverage reports.
Simulation coverage closure handles unreachable code by providing a rigorous classification system that flags it during analysis, ensuring it is properly documented as an exclusion rather than failing the regression.
Yes, you can use this to achieve 90% statement coverage for an FPGA merge by iteratively identifying and closing coverage gaps through targeted testbench stimulus to ensure design logic is exercised.
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